Patents by Inventor Naotaka Tanaka
Naotaka Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691739Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.Type: GrantFiled: March 4, 2016Date of Patent: June 27, 2017Assignee: Tessera Advanced Technologies, Inc.Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20160190102Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 9318418Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.Type: GrantFiled: May 19, 2015Date of Patent: April 19, 2016Assignee: TESSERA ADVANCED TECHNOLOGIES, INC.Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20150255374Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.Type: ApplicationFiled: May 19, 2015Publication date: September 10, 2015Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 9076700Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: GrantFiled: August 20, 2014Date of Patent: July 7, 2015Assignee: Tessera Advanced Technologies, Inc.Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20150001711Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: ApplicationFiled: August 20, 2014Publication date: January 1, 2015Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka TANAKA, Takahiro NAITO, Takashi AKAZAWA
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Publication number: 20140252576Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.Type: ApplicationFiled: October 31, 2011Publication date: September 11, 2014Applicant: Hitachi, Ltd.Inventors: Hisashi Tanie, Hiroshi Shintani, Naotaka Tanaka
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Patent number: 8816506Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: GrantFiled: December 29, 2011Date of Patent: August 26, 2014Assignee: Tessera Advanced Technologies, Inc.Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 8378459Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.Type: GrantFiled: June 8, 2010Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Yasuhiro Naka, Naotaka Tanaka, Toshihide Uematsu, Chuichi Miyazaki, Kazunari Suzuki, Yasuyuki Nakajima, Yoshiyuki Abe, Kenji Kohzu, Kosuke Kitaichi, Shinya Ogane
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Patent number: 8324736Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: GrantFiled: June 6, 2011Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20120125670Abstract: In an electronic component having a wiring and/or an electrode prepared through firing of a paste or in an electronic component having a wiring in contact with a glass or glass ceramic member, provided is an electronic component using a Cu-based wiring material which less suffers from increase in electric resistance due to oxidation, which less causes bubbles in the glass or glass ceramic, and has satisfactory migration resistance. The Cu—Al alloy powder includes a Cu—Al alloy powder including Cu and, preferably, 50 percent by weight or less of Al; and an aluminum oxide film having a thickness of 80 nm or less and being present on the surface of the Cu—Al alloy powder. The powder, when compounded with a glass or glass ceramic material to give a paste, can be used to form wiring (interconnections), electrodes, and/or contact members.Type: ApplicationFiled: August 2, 2010Publication date: May 24, 2012Inventors: Takahiko Kato, Takashi Naito, Takuya Aoyagi, Hiroki Yamamoto, Masato Yoshida, Mitsuo Katayose, Shinji Takeda, Naotaka Tanaka, Shuichiro Adachi
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Patent number: 8178977Abstract: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.Type: GrantFiled: June 12, 2009Date of Patent: May 15, 2012Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20120108055Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro YOSHIMURA, Naotaka TANAKA, Michihiro KAWASHITA, Takahiro NAITO, Takashi AKAZAWA
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Publication number: 20120091583Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: ApplicationFiled: December 29, 2011Publication date: April 19, 2012Inventors: Michihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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ADHESIVE FILM FOR SOLAR CELL ELECTRODE AND METHOD FOR MANUFACTURING SOLAR CELL MODULE USING THE SAME
Publication number: 20120048332Abstract: There are provided an adhesive film for a solar cell electrode providing a solar cell capable of reducing adverse effects on photovoltaic cells caused by heating or pressure and having sufficient solar cell characteristics, and a method for manufacturing a solar cell module using the same. The adhesive film for a solar cell electrode is an adhesive film used for electrical connection between photovoltaic cell surface electrodes and wiring members, wherein the adhesive film contains a crystalline epoxy resin, a curing agent and a film forming material.Type: ApplicationFiled: August 25, 2011Publication date: March 1, 2012Applicant: HITACHI CHEMICAL COMPANY, LTD.Inventors: Shigenori Shimizu, Hiroyuki Izawa, Keisuke Ookubo, Shigeaki Funyu, Yutaka Okada, Keiko Funyu, Naotaka Tanaka -
Patent number: 8110900Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.Type: GrantFiled: January 27, 2009Date of Patent: February 7, 2012Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
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Patent number: 8106518Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: GrantFiled: December 17, 2009Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20110233773Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 7973415Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: GrantFiled: June 5, 2008Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20110156274Abstract: The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: Renesas Technology Corp.Inventors: Kenya Kawano, Kisho Ashida, Naotaka Tanaka, Hiroshi Sato, Ichio Shimizu