Patents by Inventor Naotaka Tanaka

Naotaka Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200045616
    Abstract: The disclosure provides a communication system and a program update method. In a communication system according to the disclosure, when a host device updates a program stored in each of a plurality of communication terminals, first, the host device transmits a distribution preparation completion signal by broadcast. Each of the plurality of communication terminals transmits a start request signal to the host device in response to reception of the distribution preparation completion signal. The host device transmits a permission signal for giving a right for performing a data request to one communication terminal that has transmitted the start request signal earliest. The one communication terminal transmits a data request signal to the host device in response to reception of the permission signal. The host device transmits the update program data by broadcast to the plurality of communication terminals in response to reception of the data request signal.
    Type: Application
    Filed: July 19, 2019
    Publication date: February 6, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Yoshiyuki Tanaka, Naotaka Saito, Eiichi Saito
  • Patent number: 9691739
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 27, 2017
    Assignee: Tessera Advanced Technologies, Inc.
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20160190102
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: 9318418
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 19, 2016
    Assignee: TESSERA ADVANCED TECHNOLOGIES, INC.
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20150255374
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 10, 2015
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: 9076700
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: July 7, 2015
    Assignee: Tessera Advanced Technologies, Inc.
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20150001711
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Application
    Filed: August 20, 2014
    Publication date: January 1, 2015
    Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka TANAKA, Takahiro NAITO, Takashi AKAZAWA
  • Publication number: 20140252576
    Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.
    Type: Application
    Filed: October 31, 2011
    Publication date: September 11, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Hisashi Tanie, Hiroshi Shintani, Naotaka Tanaka
  • Patent number: 8816506
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Tessera Advanced Technologies, Inc.
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: 8378459
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Toshihide Uematsu, Chuichi Miyazaki, Kazunari Suzuki, Yasuyuki Nakajima, Yoshiyuki Abe, Kenji Kohzu, Kosuke Kitaichi, Shinya Ogane
  • Patent number: 8324736
    Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20120125670
    Abstract: In an electronic component having a wiring and/or an electrode prepared through firing of a paste or in an electronic component having a wiring in contact with a glass or glass ceramic member, provided is an electronic component using a Cu-based wiring material which less suffers from increase in electric resistance due to oxidation, which less causes bubbles in the glass or glass ceramic, and has satisfactory migration resistance. The Cu—Al alloy powder includes a Cu—Al alloy powder including Cu and, preferably, 50 percent by weight or less of Al; and an aluminum oxide film having a thickness of 80 nm or less and being present on the surface of the Cu—Al alloy powder. The powder, when compounded with a glass or glass ceramic material to give a paste, can be used to form wiring (interconnections), electrodes, and/or contact members.
    Type: Application
    Filed: August 2, 2010
    Publication date: May 24, 2012
    Inventors: Takahiko Kato, Takashi Naito, Takuya Aoyagi, Hiroki Yamamoto, Masato Yoshida, Mitsuo Katayose, Shinji Takeda, Naotaka Tanaka, Shuichiro Adachi
  • Patent number: 8178977
    Abstract: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: May 15, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20120108055
    Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro YOSHIMURA, Naotaka TANAKA, Michihiro KAWASHITA, Takahiro NAITO, Takashi AKAZAWA
  • Publication number: 20120091583
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 19, 2012
    Inventors: Michihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20120048332
    Abstract: There are provided an adhesive film for a solar cell electrode providing a solar cell capable of reducing adverse effects on photovoltaic cells caused by heating or pressure and having sufficient solar cell characteristics, and a method for manufacturing a solar cell module using the same. The adhesive film for a solar cell electrode is an adhesive film used for electrical connection between photovoltaic cell surface electrodes and wiring members, wherein the adhesive film contains a crystalline epoxy resin, a curing agent and a film forming material.
    Type: Application
    Filed: August 25, 2011
    Publication date: March 1, 2012
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Shigenori Shimizu, Hiroyuki Izawa, Keisuke Ookubo, Shigeaki Funyu, Yutaka Okada, Keiko Funyu, Naotaka Tanaka
  • Patent number: 8110900
    Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
  • Patent number: 8106518
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20110233773
    Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: 7973415
    Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: July 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa