Patents by Inventor Naotaka Tanaka

Naotaka Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070176266
    Abstract: The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.
    Type: Application
    Filed: December 15, 2006
    Publication date: August 2, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Naotaka Tanaka, Hiroshi Sato, Ichio Shimizu
  • Publication number: 20070176298
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 2, 2007
    Applicants: Hitachi, Ltd., Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
  • Publication number: 20070018320
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Application
    Filed: September 12, 2006
    Publication date: January 25, 2007
    Applicants: ROHM CO., LTD., RENESAS TECHNOLOGY CORPORATION
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka
  • Patent number: 7122457
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka
  • Publication number: 20060220230
    Abstract: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.
    Type: Application
    Filed: January 27, 2006
    Publication date: October 5, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
  • Publication number: 20060197204
    Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
    Type: Application
    Filed: April 14, 2006
    Publication date: September 7, 2006
    Applicant: Hitachi,Ltd.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
  • Publication number: 20060170112
    Abstract: A connection method for materializing a high-performance semiconductor system which is small-sized and high dense, is capable to three-dimensionally connecting a plurality of different kinds of semiconductor chips through piercing electrodes with shortest wiring lengths. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs.
    Type: Application
    Filed: January 10, 2006
    Publication date: August 3, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
  • Patent number: 7057278
    Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: June 6, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
  • Publication number: 20060043618
    Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.
    Type: Application
    Filed: June 30, 2005
    Publication date: March 2, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Kisho Ashida, Akira Muto, Ichio Shimizu, Toshiyuki Hata, Kenya Kawano, Naotaka Tanaka, Nae Hisano
  • Publication number: 20050263869
    Abstract: To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 1, 2005
    Applicants: Renesas Technology Corp., Hitachi, Ltd.
    Inventors: Naotaka Tanaka, Norio Nakazato, Takahiro Naito
  • Publication number: 20050230826
    Abstract: An object of the present invention is to manufacture a semiconductor device improved in the connection reliability between a bump electrode and a substrate electrode. Supposing that an elastic modulus of an adhesive material, which is used for the purpose of electrically connecting a metal bump and an interconnect pattern and sealing the circuit surface of LSI of an LSI chip, after thermosetting is Ea; an elastic modulus of an insulating material constituting the surface layer of a packaging substrate after thermosetting is Eb; and an elastic modulus of a core material, if the substrate is a multilayer substrate having a core layer, is Ec, the material system of the present invention satisfies the following rational expression at normal temperature or a thermal contact bonding temperature of the adhesive material: at least Ea<Eb<Ec, preferably ?Eb<Ea<Eb<3Ea(<Ec).
    Type: Application
    Filed: March 22, 2005
    Publication date: October 20, 2005
    Inventors: Naotaka Tanaka, Kenya Kawano, Akira Nagai, Koji Tasaki, Masaaki Yasuda
  • Patent number: 6911734
    Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: June 28, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
  • Patent number: 6911733
    Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: June 28, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
  • Patent number: 6897570
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 24, 2005
    Assignee: Renesas Technology, Corporation
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20050029673
    Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 10, 2005
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
  • Patent number: 6844219
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Publication number: 20050009329
    Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.
    Type: Application
    Filed: May 7, 2004
    Publication date: January 13, 2005
    Inventors: Kazumasa Tanida, Yoshihiko Nemoto, Naotaka Tanaka
  • Publication number: 20050001314
    Abstract: An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
    Type: Application
    Filed: June 23, 2004
    Publication date: January 6, 2005
    Inventors: Naotaka Tanaka, Tomio Iwasaki, Hideo Miura, Yasuyuki Nakajima, Tomoo Matsuzawa
  • Patent number: 6800945
    Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: October 5, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
  • Publication number: 20040140544
    Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 22, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito