Abstract: The SOI lateral semiconductor device includes a semiconductor region of a first conductivity type, a buried oxide film layer in the semiconductor region, a thin active layer on the buried oxide film layer, an anode region in the thin active layer, and a drain layer contacting the buried oxide film layer for confining the minority carriers injected from the anode region to the thin active layer within the thin active layer and for forming a structure that sustains a high breakdown voltage. The SOI lateral semiconductor device can provide a high breakdown voltage and low switching losses using the thin buried oxide film, which can be formed by an implanted oxygen (SIMOX) method.

Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: A plurality of trenches, about 1 ?m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.

Abstract: A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p?-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

Abstract: A semiconductor device, and method for manufacturing the same, manufactured by a simpler process, compared to a conventional trench lateral power MOSFET for a withstand voltage of 80 V, having a smaller device pitch and lower on-resistance per unit area as compared with a conventional lateral power MOSFET with a withstand voltage lower than 80 V. The semiconductor device may include a shallow and narrow trench formed in a substrate with small spacing, a drift region that is an n diffusion region formed around the trench, a gate oxide film having a uniform thickness of about 0.

Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.

Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n?-type diffusion region, which will be a drift region, on a p?-type substrate; selectively removing a part of substrate and a part of n?-type diffusion region to form trenches; forming a gate oxide film of 0.05 ?m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p?-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n?-type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

Abstract: A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage.

Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Abstract: A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p?-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: A plurality of trenches, about 1 ?m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.

Abstract: A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p−-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n−-type diffusion region.