Patents by Inventor Naoto Fujishima

Naoto Fujishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5432370
    Abstract: A semiconductor integrated circuit device is provided in which a highly reliable and low cost intelligent power semiconductor is mounted on the same substrate as that of a control circuit having a logic element, such as a low withstand voltage CMOS etc., and high withstand voltage and high current output MIS field effect transistor. A high withstand voltage MOSFET is composed of a vertical MOS portion 25 formed in one side of a laterally widened well layer 2 and a drain portion formed in the other side thereof and a second base layer 4 is formed on the surface of the well layer 2. Accordingly, a depletion layer widened just under the MOS portion 25 and the second base layer 4 develops a JFET effect at OFF time thereby realizing a high withstand voltage and reliability is provided since the generation of hot carriers can be prevented by the second base layer 4.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: July 11, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akio Kitamura, Naoto Fujishima, Gen Tada
  • Patent number: 5276339
    Abstract: In a semiconductor equipped with a conductivity modulating MISFET (IGBT) with a high withstand voltage in blocking forward and reverse directions, a withstand power is maintained in lieu of a drain wall disposed to improve the withstand power, and a current-carrying capacity, which is restricted by the drain wall, is increased. A potential at the drain wall disposed between a DMOS section and a collector section is transmitted at a portion between the collector section and an isolation layer by an channel stop electrode (201) that maintains the withstand power, while an increase in the current-carrying capacity is achieved by forming a conductivity modulating layer alone between the above section.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: January 4, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Naoto Fujishima
  • Patent number: 4933573
    Abstract: An improved semiconductor integrated circuit included in electrical equipment for recharging and discharging a load capacitor with alternating current and which includes differentiating circuits inherently formed in the integrated circuit and whose devices are formed on a P-type substrate and are isolated from each other by PN junction isolation. The substrate of the integrated circuit is electrically isolated from any grounding electrodes and is connected to a negative voltage source.
    Type: Grant
    Filed: September 14, 1988
    Date of Patent: June 12, 1990
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hisao Takeda, Naoto Fujishima