Abstract: A high-voltage and low on-resistance semiconductor device incorporates a trench structure that provides improved switching characteristics. In a preferred embodiment, a Trench Lateral Power MISFET is provided having a gate, channel and drift regions that are built on the side-walls of the trench. The process used to form the MISFET involves a self-aligned trench bottom contact hole to contact a source provided at the bottom of the trench to achieve minimum pitch and very low on-resistance. An example of a MISFET with 80 V breakdown voltage having a cell pitch of 3.4 microns is disclosed in which an on-resistance of 0.7 m&OHgr;-cm2 is realized. The switching characteristics of the MISFET are twice as good as that of prior MISFET device structures.

Abstract: The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region.

Abstract: A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage.

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage.

Abstract: A lateral field effect transistor improves the trade-off relationship between the breakdown voltage and on-resistance of a lateral MOSFET integrated into a power IC. A MOSFET is formed by forming a p-type well region on a p-type substrate, and an n-type drain region accompanying an n-type offset region on the well region. A thick oxide film is disposed on the offset region. The surface concentration of the offset region is, preferably, from 5.times.10.sup.16 to 2.times.10.sup.17 cm.sup.-3 and the diffusion depth thereof is from 0.5 to 1.5 .mu.m. The maximum impurity concentration of a p-type well region is preferably adjusted to be from 5.times.10.sup.15 to 3.times.10.sup.16 cm.sup.-3. By the shallow junction depth of the offset region that promotes depletion thereof, the breakdown voltage is increased. Also, by the high maximum impurity concentration of the well region of from 5.times.10.sup.15 to 3.times.10.sup.16 cm.sup.-3, the on-resistance is lowered.

Abstract: To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Abstract: A high withstand-voltage lateral MOSFET with a trench includes a first conductive type semiconductor layer; a second conductive type source region; a second conductive type drain drift region, the second conductive type source region and the second conductive type drain drift region being formed in a portion of a surface layer of the first conductive type semiconductor layer at a distance from each other; a trench which formed in a surface layer of the second conductive type drain drift region from the surface side thereof; a second conductive type drain region formed in the surface layer of the first conductive type semiconductor layer on the side opposite to the second conductive type source region with respect to the trench and partially overlaps with the second conductive type drain drift region; a gate electrode provided on the surface of a surface exposed portion of the first conductive type semiconductor layer through a gate oxide film; a source electrode provided on the surface of the second conductiv

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: A back-source MOSFET uses a source electrode on a second surface of a substrate to reduce noise which would otherwise interfere with the logic circuit of a power integrated circuit. One embodiment includes a substrate of a first conductivity type and a base layer of a second conductivity type on a first surface of the substrate. A source region is electrically connected with the substrate. A source electrode is formed on a second surface of the substrate. A further embodiment includes a substrate of a first conductivity type and a base layer of a first conductivity type on a first surface of the substrate. A source electrode is formed on a second surface of the substrate.

Abstract: A method of manufacturing a BiCMOS apparatus including a DMOS is disclosed which reduces manufacturing steps, shortens manufacturing time and reduces manufacturing cost. A channel ion implanted layer is formed by implanting acceptor impurities from the surface of a P-type well 5. A poly-silicon gate electrode is formed on gate insulation film and local oxide film. Impurity ions are then implanted for forming P-type base region by employing the bipolar transistor process and by using the gate electrode as a mask. Then, side walls are formed at high temperature on both sides of the gate electrode by employing the CMOS process of forming the LDD structure. At the same time, the P-type base region is formed by diffusing the implanted impurity ions. An N.sup.+ -type source region is then formed self-aligned by employing the CMOS process for forming the N.sup.+ -type source and drain of the CMOS transistor and by using the gate electrode 10 as a mask for the self alignment.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.

Abstract: To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Abstract: A lateral field effect transistor includes a semiconductor substrate, a source region further with source region stripes formed on the semiconductor substrate, and a drain region with drain region stripes formed on the semiconductor substrate and spaced laterally from the source region stripes. In addition, the lateral field effect transistor includes a source electrode having a first source electrode layer connected to the source region via a source contact and a second source electrode layer straddling the source region stripes and the drain region stripes. The first source electrode layer and the second source electrode layer are separated by an inter-layer insulation film and connected via a source connection hole formed through the inter-layer insulation film.

Abstract: A semiconductor device with a metal-insulator-semiconductor transistor and a limiter or sacrifice diode has predetermined breakdown voltage and constant withstand voltage. The device includes a special well region underlying a drain portion or contacting an edge of a drain portion.

Abstract: The invention increases withstand voltage and current capacity of a DMOS portion simultaneously built in by the BiCMOS process. The manufacturing method for the DMOS portion is comprised of steps of forming an ion-implanted layer in a surface of a P-type well; forming a gate electrode; self-aligning a P-type base region by employing the P-type base formation process of the bipolar transistor and by using the gate electrode as a mask; forming a side wall on a side face of the gate electrode by employing the process for forming the LDD structure of the CMOS; and self-aligning an N+type source region by employing the process for forming the N+type source and the drain of the CMOS and by using the side wall as a mask. The effective channel length becomes longer by the side wall length and the rate of heavily doped channel portion to the total channel length becomes high.

Abstract: A high voltage MIS field effect transistor includes a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on an obverse surface side of the semiconductor substrate; a base layer of the first conductivity type formed in the semiconductor layer; a source layer of the second conductivity type formed in the base layer; a source electrode abutting the source layer; a gate electrode formed in such a manner as to extend from the source layer to the semiconductor layer via an insulating gate film; a drain section including a drain layer of the second conductivity type formed in the semiconductor layer in such a manner as to be spaced apart from the source layer; and a low-concentration region of the first conductivity type being formed in a vicinity of a periphery of a base corner portion of said base layer.

Abstract: To widen the width of under layer wiring connected to a source region and to lower the resistance of the under layer wiring in a semiconductor device, a direction connecting a through hole with a contact hole connected to a drain region is tilted by 45 or by 30 over a direction connecting between contact holes for connecting a source region or the drain region. Alternatively, the source region and the a drain region are respectively aligned in parallel stripes, and the through hole and the contact hole for connecting the drain region are aligned in a stripe in which the drain region is aligned.

Abstract: On-resistance is minimized in a high-current integrated circuit by efficient use of wiring spaces for various layers in a wiring construction with multilayer-wiring connections between transistor electrode regions and electrode terminals. The construction utilizes multiple wiring layers and interlayer insulation films between the wiring layers, which insulation films have connecting holes at specified portions of the wiring structure. By incorporating connecting holes at select locations, and utilizing spaces which are not used for connecting holes as spaces for routing different wiring layers, the wiring structure allows overlapping wiring connections between the transistor electrode regions and the electrode terminals.

Abstract: A high voltage MIS transistor includes a well region of a second conduction type formed by a step of injecting ions from the surface side of a semiconductor substrate of a first conduction type and a thermal diffusion step after the ion injecting step; an MIS part including a base layer of a first conduction type formed in one end portion of the well region, a base contact layer of a first conduction type which is formed in the base layer of a first conduction type and to which an emitter potential is applied, and a gate electrode provided so as to extend from an emitter layer of a second conduction type to the well region through an insulation gate film; and, a collector part including a base layer of a second conduction type formed in the other end portion of the well region, a collector layer of a first conduction type formed in the base layer of a second conduction type, and a high concentration contact layer of a first conduction type which is formed in the collector layer and to which a collector potent