Patents by Inventor Naoto Kusumoto
Naoto Kusumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150287660Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.Type: ApplicationFiled: May 28, 2015Publication date: October 8, 2015Inventors: Ryosuke WATANABE, Naoto KUSUMOTO, Osamu NAKAMURA
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Publication number: 20150279884Abstract: An imaging device which is capable of taking images with high quality and can be manufactured at low cost is provided. An imaging device includes a first layer, a third layer and a second layer which is located between the first layer and the second layer. The first layer includes a first transistor, the second layer includes a second transistor, and the third layer includes a photodiode. A channel formation region of the first transistor includes silicon. A channel formation region of the second transistor includes an oxide semiconductor. The photodiode has a PIN structure and includes amorphous silicon.Type: ApplicationFiled: March 25, 2015Publication date: October 1, 2015Inventor: Naoto KUSUMOTO
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Patent number: 9095066Abstract: A printed board is provided, which includes at least a first connecting electrode and a second connecting electrode. A solder is provided over the first connecting electrode and the second connecting electrode, and a chip component is provided over the solder. The chip component includes a first terminal electrode and a second terminal electrode. The first connecting electrode is overlapped with the first terminal electrode and is electrically connected to the first terminal electrode through the solder. The second connecting electrode is overlapped with the second terminal electrode and is electrically connected to the second terminal electrode through the solder. Two corner portions of each of the first connecting electrode and the second connecting electrode are overlapped with two corner portions of each of the first terminal electrode and the second terminal electrode.Type: GrantFiled: June 11, 2009Date of Patent: July 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Naoto Kusumoto
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Patent number: 9059347Abstract: A photoelectric conversion device having a high electric generating capacity at low illuminance, in which a semiconductor layer is appropriately separated and short circuit of a side surface portion of a cell is prevented. The photoelectric conversion device includes an isolation groove formed between one first electrode and the other first electrode that is adjacent to the one first electrode; a stack including a first semiconductor layer having one conductivity type over the first electrode, a second semiconductor layer formed using an intrinsic semiconductor, and a third semiconductor layer having a conductivity type opposite to the one conductivity type; and a connection electrode connecting one first electrode and a second electrode that is in contact with a third semiconductor layer included in a stack formed over the other first electrode that is adjacent to the one first electrode. A side surface portion of the second semiconductor layer is not crystallized.Type: GrantFiled: June 14, 2011Date of Patent: June 16, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Takashi Hirose, Naoto Kusumoto
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Publication number: 20150162477Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.Type: ApplicationFiled: February 20, 2015Publication date: June 11, 2015Inventors: Takashi HIROSE, Naoto KUSUMOTO
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Patent number: 9053401Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.Type: GrantFiled: July 28, 2005Date of Patent: June 9, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Ryosuke Watanabe, Naoto Kusumoto, Osamu Nakamura
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Publication number: 20150123121Abstract: A semiconductor device with a structure in which an increase in the number of oxygen vacancies in an oxide semiconductor layer can be suppressed and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an oxide insulating layer; intermediate layers apart from each other over the oxide insulating layer; a source electrode layer and a drain electrode layer over the intermediate layers; an oxide semiconductor layer that is electrically connected to the source electrode layer and the drain electrode layer and is in contact with the oxide insulating layer; a gate insulating film over the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate electrode layer that is over the gate insulating film and overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.Type: ApplicationFiled: November 4, 2014Publication date: May 7, 2015Inventors: Kazuya Hanaoka, Naoto Kusumoto
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Patent number: 8987738Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.Type: GrantFiled: September 27, 2012Date of Patent: March 24, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takashi Hirose, Naoto Kusumoto
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Patent number: 8963148Abstract: Provided is a semiconductor device having a structure which can suppress a decrease in electrical characteristics, which becomes more significant with miniaturization. The semiconductor device includes a plurality of gate electrode layers separated from each other. One of the plurality of gate electrode layers includes a region which overlaps with a part of an oxide semiconductor layer, a part of a source electrode layer, and a part of a drain electrode layer. Another of the plurality of gate electrode layers overlaps with a part of an end portion of the oxide semiconductor layer. The length in the channel width direction of each of the source electrode layer and the drain electrode layer is shorter than that of the one of the plurality of gate electrode layers.Type: GrantFiled: November 14, 2013Date of Patent: February 24, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daisuke Matsubayashi, Satoshi Shinohara, Wataru Sekine, Naoto Kusumoto
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Publication number: 20140326992Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.Type: ApplicationFiled: April 22, 2014Publication date: November 6, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Suguru HONDO, Kazuya HANAOKA, Shinya SASAGAWA, Naoto KUSUMOTO
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Publication number: 20140131702Abstract: Provided is a semiconductor device having a structure which can suppress a decrease in electrical characteristics, which becomes more significant with miniaturization. The semiconductor device includes a plurality of gate electrode layers separated from each other. One of the plurality of gate electrode layers includes a region which overlaps with a part of an oxide semiconductor layer, a part of a source electrode layer, and a part of a drain electrode layer. Another of the plurality of gate electrode layers overlaps with a part of an end portion of the oxide semiconductor layer. The length in the channel width direction of each of the source electrode layer and the drain electrode layer is shorter than that of the one of the plurality of gate electrode layers.Type: ApplicationFiled: November 14, 2013Publication date: May 15, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daisuke Matsubayashi, Satoshi Shinohara, Wataru Sekine, Naoto Kusumoto
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Patent number: 8698262Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.Type: GrantFiled: August 30, 2005Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
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Patent number: 8648439Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.Type: GrantFiled: April 18, 2013Date of Patent: February 11, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto
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Patent number: 8592936Abstract: A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted.Type: GrantFiled: June 21, 2012Date of Patent: November 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoto Kusumoto, Kazuo Nishi, Yuusuke Sugawara
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Patent number: 8574976Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.Type: GrantFiled: October 14, 2010Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Naoto Kusumoto, Hideto Ohnuma, Koichiro Tanaka
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Patent number: 8557614Abstract: An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.Type: GrantFiled: December 23, 2011Date of Patent: October 15, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai, Naoto Kusumoto
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Publication number: 20130228885Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.Type: ApplicationFiled: April 18, 2013Publication date: September 5, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshitaka DOZEN, Tomoyuki AOKI, Hidekazu TAKAHASHI, Daiki YAMADA, Eiji SUGIYAMA, Kaori OGITA, Naoto KUSUMOTO
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Patent number: 8492246Abstract: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.Type: GrantFiled: June 17, 2011Date of Patent: July 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Naoto Kusumoto, Takuya Tsurume
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Patent number: 8481370Abstract: The present invention provides a semiconductor device having a structure that can be mounted on a wiring substrate, as for the semiconductor device formed over a thin film-thickness substrate, a film-shaped substrate, or a sheet-like substrate. In addition, the present invention provides a method for manufacturing a semiconductor device that is capable of raising a reliability of mounting on a wiring substrate. One feature of the present invention is to bond a semiconductor element formed on a substrate having isolation to a member that a conductive film is formed via a medium having an anisotropic conductivity.Type: GrantFiled: August 3, 2006Date of Patent: July 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Hiroki Adachi, Naoto Kusumoto, Yuusuke Sugawara, Hidekazu Takahashi, Daiki Yamada, Yoshikazu Hiura
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Patent number: 8432018Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.Type: GrantFiled: October 12, 2011Date of Patent: April 30, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto