Patents by Inventor Naoya Inoue

Naoya Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150349134
    Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventors: Hiroshi SUNAMURA, Naoya INOUE, Kishou Kaneko
  • Patent number: 9159618
    Abstract: A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: October 13, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Hijioka, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20150287832
    Abstract: A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya INOUE, Kishou KANEKO
  • Patent number: 9153588
    Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 6, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko
  • Patent number: 9129937
    Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Publication number: 20150214218
    Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: Kishou KANEKO, Naoya INOUE, Yoshihiro HAYASHI
  • Patent number: 9085215
    Abstract: An estimated temperature range is calculated by adding a plus-side temperature width to the temperature detected by a temperature sensor within the cabin of a vehicle and subtracting a minus-side temperature width therefrom, and is displayed on the display of a mobile terminal as a temperature state of the cabin. When cooling is performed, the plus-side temperature width is made greater than the minus-side temperature width. Also, the plus-side temperature width is narrowed with elapse of time from the start of pre-air-conditioning. With this operation, the temperature state of the vehicle cabin from the start of the pre-air-conditioning can be properly communicated to a vehicle user.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 21, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirohito Kawai, Naoya Inoue, Seiichi Tsunoda, Takaaki Goto, Yoichiro Higuchi
  • Publication number: 20150200135
    Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
    Type: Application
    Filed: March 25, 2015
    Publication date: July 16, 2015
    Inventors: Hiroshi SUNAMURA, Naoya INOUE, Kishou KANEKO
  • Publication number: 20150171120
    Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Inventors: Kishou KANEKO, Naoya INOUE, Yoshihiro HAYASHI
  • Patent number: 9059137
    Abstract: A semiconductor device, includes a semiconductor substrate, a first interconnect layer formed over the semiconductor substrate, a gate electrode formed in the first interconnect layer, a gate insulating film formed over the gate electrode, a second interconnect layer formed over the gate insulating film, an oxide semiconductor layer formed in the second interconnect layer, and a via formed in the second interconnect layer and connected to the oxide semiconductor layer. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 16, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Patent number: 9053961
    Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: June 9, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 9048291
    Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: June 2, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Inoue, Kishou Kaneko, Yoshihiro Hayashi
  • Patent number: 9035360
    Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 9000540
    Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko
  • Patent number: 8987729
    Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20150056778
    Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 26, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Kenzo MANABE, Naoya INOUE, Kenichiro HIJIOKA, Yoshihiro HAYASHI
  • Publication number: 20150056762
    Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Naoya INOUE, Kishou KANEKO, Yoshihiro HAYASHI
  • Patent number: 8946800
    Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: February 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
  • Publication number: 20150024593
    Abstract: A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film.
    Type: Application
    Filed: August 1, 2014
    Publication date: January 22, 2015
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20140357047
    Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.
    Type: Application
    Filed: August 13, 2014
    Publication date: December 4, 2014
    Inventors: Jun KAWAHARA, Naoya INOUE, Naoya FURUTAKE, Yoshihiro HAYASHI