Patents by Inventor Naoya Inoue

Naoya Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8901553
    Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Kishou Kaneko, Yoshihiro Hayashi
  • Patent number: 8890289
    Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Manabe, Naoya Inoue, Kenichiro Hijioka, Yoshihiro Hayashi
  • Patent number: 8862326
    Abstract: In a vehicle travel assisting device, a vehicle speed, a yaw rate, a traveling lane of an own vehicle, and a position of a leading vehicle are detected. Target travel coordinates of the own vehicle are calculated, based on the traveling lane and the position of the leading vehicle A travel path curvature of a target travel coordinate group is estimated, based on information related to the target travel coordinate group. A steering quantity to be steered in advance by the own vehicle is calculated, based on the currently estimated travel path curvature. A weight for each of the target travel coordinates for estimating the travel path curvature is adjusted based on the vehicle speed, the yaw rate and the previously estimated travel path curvature. Steering control is performed such that the own vehicle travels so as to follow the estimated travel path curvature, based on the calculated steering quantity.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: October 14, 2014
    Assignee: Denso Corporation
    Inventors: Tomohiko Tsuruta, Yusuke Ueda, Takeshi Hatoh, Takayuki Kondoh, Naoya Inoue
  • Publication number: 20140295657
    Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.
    Type: Application
    Filed: June 10, 2014
    Publication date: October 2, 2014
    Inventors: Naoya INOUE, Kishou KANEKO, Yoshihiro HAYASHI
  • Publication number: 20140281033
    Abstract: An information processing apparatus includes a receiving unit configured to receive request data to an application via a global network allocated to the information processing apparatus, the request data including a global address specified as a destination address; a determination unit configured to determine, based on the request data, whether the application is to be executed by another apparatus connected via a private network and allocated with a private address; a change unit configured to change the destination address in the request data from the global address of the information processing apparatus to the private address of the another apparatus when the determination unit determines that the application is to be executed by the another apparatus; and a transmission unit configured to transfer, to the another apparatus, the request data including the private address of the another apparatus as the destination address.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: Ricoh Company, Ltd.
    Inventor: Naoya Inoue
  • Patent number: 8835190
    Abstract: A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 16, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8829649
    Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Kawahara, Naoya Inoue, Naoya Furutake, Yoshihiro Hayashi
  • Patent number: 8810000
    Abstract: A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8803285
    Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroto Ohtake, Naoya Inoue, Ippei Kume, Takeshi Toda, Yoshihiro Hayashi
  • Patent number: 8791751
    Abstract: A semiconductor integrated circuit includes a logic circuit having a plurality of operation modes, a power source circuit that generates a power source voltage to be supplied to the logic circuit, a power source wiring that couples the power source circuit and the logic circuit, and a charge control block that holds charges for controlling the voltage of the power source wiring. The power source circuit generates a first power source voltage for causing the logic circuit to operate in a computing mode and a second power source voltage for causing the logic circuit to operate in a sleep mode. The charge control block includes a capacitor, a first switch, and a voltage supply unit that supplies the second power source voltage or a third power source voltage lower than the second power source voltage, to the capacitor.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Ueki, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20140200768
    Abstract: In a vehicle travel assisting device, a vehicle speed, a yaw rate, a traveling lane of an own vehicle, and a position of a leading vehicle are detected. Target travel coordinates of the own vehicle are calculated, based on the traveling lane and the position of the leading vehicle A travel path curvature of a target travel coordinate group is estimated, based on information related to the target travel coordinate group. A steering quantity to be steered in advance by the own vehicle is calculated, based on the currently estimated travel path curvature. A weight for each of the target travel coordinates for estimating the travel path curvature is adjusted based on the vehicle speed, the yaw rate and the previously estimated travel path curvature. Steering control is performed such that the own vehicle travels so as to follow the estimated travel path curvature, based on the calculated steering quantity.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 17, 2014
    Applicant: DENSO CORPORATION
    Inventors: Tomohiko Tsuruta, Yusuke Ueda, Takeshi Hatoh, Takayuki Kondoh, Naoya Inoue
  • Publication number: 20140200801
    Abstract: When a travel path is to be generated for a vehicle, road surface lines (white lines, etc.) delimiting the traffic lane of the vehicle, and also external objects in the vehicle environment, are detected and registered as respective obstacles. Specific points are defined at appropriate locations on each obstacle, and the travel path is generated by connecting respective mid-point positions between opposed pairs of specific points, each pair defined on respective ones of an opposed (left-side, right-side) pair of the registered obstacles.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Applicant: DENSO CORPORATION
    Inventors: Tomohiko Tsuruta, Yusuke Ueda, Takeshi Hatoh, Takayuki Kondoh, Naoya Inoue, Hossein Tehrani Niknejad, Seiichi Mita
  • Patent number: 8779594
    Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Kishou Kaneko, Yoshihiro Hayashi
  • Publication number: 20140187047
    Abstract: A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayoshi TAGAMI, Naoya INOUE
  • Publication number: 20140180543
    Abstract: In a vehicle control device, a basic steering amount calculation section calculates a basic steering amount to drive an own vehicle on a basic route along a driving lave. A posture detection section detects a vehicle posture state indicated by a lateral position and an angle of yaw. An offset distance detection section detects an offset distance between the basis route and the lateral position. A correction steering amount calculation section calculates a correction steering amount as a steering control amount to drive the own vehicle along a virtual correction route. The posture of the own vehicle is alien with a predetermined target posture at a predetermined virtual target point by using the virtual correction route. An instruction steering amount calculation section calculates an instruction steering amount on the basis of the basic steering amount and the correction steering amount.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 26, 2014
    Applicant: DENSO CORPORATION
    Inventors: Yusuke Ueda, Tomohiko Tsuruta, Takeshi Hatoh, Takayuki Kondoh, Naoya Inoue
  • Publication number: 20140180569
    Abstract: A selection track setting section in a driving route generation device determines as a selected track a track of a preceding vehicle when a detection section and a track generation section detects a track of the preceding vehicle which is running on the same driving lane of a host vehicle. A candidate track selection section outputs as a candidate track one of tracks of front vehicles, detected by the detection section and the track generation section, other than the track of the preceding vehicle. A switching selection section switches as the selected track from the track of the preceding vehicle to the candidate track when a detection of the track of the preceding vehicle is interrupted during a predetermined detection period. An estimate route generation section generates an estimated driving route of the host vehicle on the bass of the selected track.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 26, 2014
    Applicant: DENSO CORPORATION
    Inventors: Yusuke Ueda, Tomohiko Tsuruta, Takeshi Hatoh, Takayuki Kondoh, Naoya Inoue
  • Patent number: 8742521
    Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 3, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Ueki, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20140100716
    Abstract: An estimated temperature range is calculated by adding a plus-side temperature width to the temperature detected by a temperature sensor within the cabin of a vehicle and subtracting a minus-side temperature width therefrom, and is displayed on the display of a mobile terminal as a temperature state of the cabin. When cooling is performed, the plus-side temperature width is made greater than the minus-side temperature width. Also, the plus-side temperature width is narrowed with elapse of time from the start of pre-air-conditioning. With this operation, the temperature state of the vehicle cabin from the start of the pre-air-conditioning can be properly communicated to a vehicle user.
    Type: Application
    Filed: May 18, 2011
    Publication date: April 10, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirohito Kawai, Naoya Inoue, Seiichi Tsunoda, Takaaki Goto, Yoichiro Higuchi
  • Publication number: 20140080228
    Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Makoto UEKI, Naoya INOUE, Yoshihiro HAYASHI
  • Patent number: 8664769
    Abstract: An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko