Patents by Inventor Naoya Sakamoto
Naoya Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8399356Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.Type: GrantFiled: March 20, 2009Date of Patent: March 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Naoya Sakamoto, Takahiro Sato, Yoshiaki Oikawa, Rai Sato, Yamato Aihara, Takayuki Cho, Masami Jintyou
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Publication number: 20120205700Abstract: The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.Type: ApplicationFiled: February 7, 2012Publication date: August 16, 2012Inventors: Yoshifumi Tanada, Naoya Sakamoto, Hiroki Adachi, Shingo Eguchi, Koji Ono, Kensuke Yoshizumi, Hiroto Shinoda
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Publication number: 20120129287Abstract: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide, concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Toru Takayama, Naoya Sakamoto, Kengo Akimoto, Keiji Sato, Tetsunori Maruyama
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Patent number: 8129900Abstract: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.Type: GrantFiled: September 26, 2008Date of Patent: March 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Naoya Sakamoto, Kengo Akimoto, Keiji Sato, Tetsunori Maruyama
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Publication number: 20090305503Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.Type: ApplicationFiled: March 20, 2009Publication date: December 10, 2009Inventors: Naoya Sakamoto, Takahiro Sato, Yoshiaki Oikawa, Rai Sato, Yamato Aihara, Takayuki Cho, Masami Jintyou
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Patent number: 7492090Abstract: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.Type: GrantFiled: September 10, 2004Date of Patent: February 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Naoya Sakamoto, Kengo Akimoto, Keiji Sato, Tetsunori Maruyama
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Publication number: 20090042326Abstract: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.Type: ApplicationFiled: September 26, 2008Publication date: February 12, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Toru Takayama, Naoya Sakamoto, Kengo Akimoto, Keiji Sato, Tetsunori Maruyama
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Patent number: 7476577Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: October 17, 2006Date of Patent: January 13, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Publication number: 20090011611Abstract: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.Type: ApplicationFiled: May 30, 2008Publication date: January 8, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Mitsuhiro ICHIJO, Tetsuhiro TANAKA, Takashi OHTSUKI, Seiji YASUMOTO, Kenichi OKAZAKI, Shunpei YAMAZAKI, Naoya SAKAMOTO
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Patent number: 7247882Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: January 14, 2005Date of Patent: July 24, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20070034870Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: ApplicationFiled: October 17, 2006Publication date: February 15, 2007Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 7132686Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: December 8, 2005Date of Patent: November 7, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Publication number: 20060113543Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: ApplicationFiled: December 8, 2005Publication date: June 1, 2006Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 7015505Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: October 14, 2003Date of Patent: March 21, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 6960787Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: August 1, 2003Date of Patent: November 1, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20050158929Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: ApplicationFiled: January 14, 2005Publication date: July 21, 2005Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20050093432Abstract: According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.Type: ApplicationFiled: September 10, 2004Publication date: May 5, 2005Inventors: Shunpei Yamazaki, Toru Takayama, Naoya Sakamoto, Kengo Akimoto, Keiji Sato, Tetsunori Maruyama
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Publication number: 20040080481Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled.Type: ApplicationFiled: August 1, 2003Publication date: April 29, 2004Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20040079952Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: ApplicationFiled: October 14, 2003Publication date: April 29, 2004Applicant: Semiconductor Energy LaboratoryInventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 6645826Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: March 7, 2002Date of Patent: November 11, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai