Patents by Inventor Naoya Sakamoto
Naoya Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6603453Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: August 28, 2002Date of Patent: August 5, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20030001832Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled.Type: ApplicationFiled: August 28, 2002Publication date: January 2, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Publication number: 20020167007Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: ApplicationFiled: March 7, 2002Publication date: November 14, 2002Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 6479334Abstract: A thin film transistor and a semiconductor device and a method for forming the same. A silicon thin film formed on an insulating substrate is heated at 550 to 800° C. so that it has crystallinity, and a thin film transistor is formed using the crystalline silicon film thus obtained. Thermal contraction of the insulating substrate is set in a range of 30 to 500 ppm in the heating process, so that the thin film transistor has high mobility, low threshold voltage and high off-resistance. Thermal contraction of the insulating substrate may be also set 100 ppm or less in a heating process after a patterning treatment in a thin film transistor producing process.Type: GrantFiled: November 22, 1999Date of Patent: November 12, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsufumi Codama, Yukio Yamauchi, Naoya Sakamoto, Takeshi Fukada
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Patent number: 6462723Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.Type: GrantFiled: June 11, 1999Date of Patent: October 8, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Setsuo Nakajima, Naoya Sakamoto
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Patent number: 6452212Abstract: A semiconductor device comprising an active layer made from a crystalline silicon formed on a substrate having an insulating surface; a gate insulating film formed on said active layer; and a source region and a drain region provided in contact with said active layer; wherein, said active layer generates photo carriers upon irradiation of a light, a part of the thus generated photo carriers having the opposite polarity with respect to that of the carriers flowing in the vicinity of the interface with the gate insulating film is temporarily accumulated within said active layer to change the resistance of the region of said active layer, and the light irradiated to said active layer is detected from the change in current flow between the source and the drain which occurs in accordance with the change in resistance in the region of said active region.Type: GrantFiled: September 19, 1997Date of Patent: September 17, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsufumi Codama, Kazushi Sugiura, Yukio Yamauchi, Naoya Sakamoto, Michio Arai
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Patent number: 6410960Abstract: A hybrid (composite) integrated circuit element comprises a substrate, a thin film type integrated circuit formed on a substrate through a thin film process, and a lamination type passive circuit element such as a capacitor, inductor, resitance and a combination thereof formed on the integrated circuit. During the firing of passive circuit element in a hydrogen atmosphere, the semiconductor layer which constitutes the integrated circuit is also heat annealed. Various substrates can be used as the substrate, for example, quartz, ceramic and a cheap semiconductor substrate which has not been treated with a mirror-grinding by the use of a glass layer.Type: GrantFiled: January 7, 1999Date of Patent: June 25, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Michio Arai, Yukio Yamauchi, Naoya Sakamoto, Katsuto Nagano
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Patent number: 6380558Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: December 23, 1999Date of Patent: April 30, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
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Patent number: 6100860Abstract: An image display device having a plurality of pixcels with uniform light intensity comprises an organic EL element (3), a bias FET (2) for emit current control of said EL element, a capacitor (4) coupled with a gate electrode of said bias FET (2) for holding a signal, and a select FET (1) for selectively writing a signal to said capacitor (4), wherein the value S of said bias FET (2) is larger than that of said select FET (1).Type: GrantFiled: May 4, 1998Date of Patent: August 8, 2000Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.Inventors: Ichiro Takayama, Kazushi Sugiura, Yukio Yamauchi, Naoya Sakamoto, Mitsufumi Codama, Michio Arai
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Patent number: 6008076Abstract: A thin film transistor and a semiconductor device and a method for forming the same. A silicon thin film formed on an insulating substrate is heated at 550 to 800.degree. C. so that it has crystallinity, and a thin film transistor is formed using the crystalline silicon film thus obtained. Thermal contraction of the insulating substrate is set in a range of 30 to 500 ppm in the heating process, so that the thin film transistor has high mobility, low threshold voltage and high off-resistance. Thermal contraction of the insulating substrate may be also set 100 ppm or less in a heating process after a patterning treatment in a thin film transistor producing process.Type: GrantFiled: November 6, 1996Date of Patent: December 28, 1999Assignee: Semicoductor Energy Laboratory Co., Ltd.Inventors: Mitsufumi Codama, Yukio Yamauchi, Naoya Sakamoto, Takeshi Fukada
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Patent number: 5952450Abstract: A crosslinked polycarbonate is obtained by polycondensation of diol (A), trivalent or more polyhydric alcohol (B) whose arbitrary two hydroxy groups are not in the positional relationship of 1,2-disubstitution or 1,3-disubstitution, and carbonyl component (C) such as carbonic acid diesters. In the polycondensation step, no side reaction does not occur.This crosslinked polycarbonate is used as a modifier for polylactic acids. The brittleness of the polylactic acid is improved while maintaining mechanical strength, thermostability, and transparency.Type: GrantFiled: July 31, 1998Date of Patent: September 14, 1999Assignees: Shimadzu Corporation, Mitsui Chemicals, Inc.Inventors: Jiro Ishihara, Hiroki Kuyama, Eiichi Ozeki, Takeshi Ishitoku, Masahide Tanaka, Naoya Sakamoto
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Patent number: 5877533Abstract: A hybrid (composite) integrated circuit element comprises a substrate, a thin film type integrated circuit formed on a substrate through a thin film process, and a lamination type passive circuit element such as a capacitor, inductor, resitance and a combination thereof formed on the integrated circuit. During the firing of passive circuit element in a hydrogen atmosphere, the semiconductor layer which constitutes the integrated circuit is also heat annealed. Various substrates can be used as the substrate, for example, quartz, ceramic and a cheap semiconductor substrate which has not been treated with a mirror-grinding by the use of a glass layer.Type: GrantFiled: March 6, 1997Date of Patent: March 2, 1999Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK CorporationInventors: Michio Arai, Yukio Yamauchi, Naoya Sakamoto, Katsuto Nagano
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Patent number: 5821560Abstract: A thin film transistor which includes an insulation base, first and second gate electrodes, first and second insulation layers, an active layer of semiconductor material, a source electrode and a drain electrode, in which a lateral length of the first gate electrode is narrower than a lateral length of the second gate electrode. Also, the first gate is electrically insulated from the active layer of semiconductor material by the first insulation layer so that the drain current saturates in a high drain voltage region.Type: GrantFiled: March 1, 1996Date of Patent: October 13, 1998Assignees: TKD Corporation, Semiconductor Energy Laboratory Co., Ltd.Inventors: Michio Arai, Kazushi Sugiura, Ichiro Takayama, Yukio Yamauchi, Isamu Kobori, Mitsufumi Codama, Naoya Sakamoto
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Patent number: 5643804Abstract: A hybrid (composite) integrated circuit element comprises a substrate, a thin film type integrated circuit formed on a substrate through a thin film process, and a lamination type passive circuit element such as a capacitor, inductor, resitance and a combination thereof formed on the integrated circuit. During the firing of passive circuit element in a hydrogen atmosphere, the semiconductor layer which constitutes the integrated circuit is also heat annealed. Various substrates can be used as the substrate, for example, quartz, ceramic and a cheap semiconductor substrate which has not been treated with a mirror-grinding by the use of a glass layer.Type: GrantFiled: May 16, 1994Date of Patent: July 1, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Michio Arai, Yukio Yamauchi, Naoya Sakamoto, Katsuto Nagano
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Patent number: 5591988Abstract: A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5') is partially provided on said active layer through a gate insulation layer (4). Said active layer (3') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1).Type: GrantFiled: June 7, 1995Date of Patent: January 7, 1997Assignees: TDK Corporation, Semiconductor Energy Lab. Co. Ltd.Inventors: Michio Arai, Takashi Inushima, Mitsufumi Codama, Kazushi Sugiura, Ichiro Takayama, Isamu Kobori, Yukio Yamauchi, Naoya Sakamoto
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Patent number: 5576222Abstract: An image sensor (10) has a substrate (1), an active layer (3') having a source region and a drain region placed on said substrate (1), a gate insulation layer (4') placed on said active layer, and a gate electrode layer (5') on said gate insulation layer (4'). The active layer (3') is produced by the steps of producing amorphous silicon layer by using disilane gas (Si.sub.2 H.sub.6) through Low Pressure CVD process, and annealing said layer at 500.degree.-650.degree. C. for 4-50 hours in nitrogen gas atmosphere. The gate insulation layer (4') is produced through oxidation of the surface of the active layer at high temperature around 900.degree.-1100.degree. C. The oxidation process at high temperature improves the anneal process and improves the active layer. Thus, an image sensor with uniform characteristics is obtained with improved producing yield rate.Type: GrantFiled: October 18, 1994Date of Patent: November 19, 1996Assignees: TDK Corp., Semiconductor Energy Laboratory Co. Ltd.Inventors: Michio Arai, Masaaki Ikeda, Kazushi Sugiura, Nobuo Furukawa, Mitsufumi Kodama, Yukio Yamauchi, Naoya Sakamoto, Takeshi Fukada, Masaaki Hiroki, Ichirou Takayama
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Patent number: 5574293Abstract: A substrate (1) has a surface covered with an insulation layer (2), on which an active layer (3') made of non-single crystal silicon through thin film technique is provided. A gate electrode layer (5') is partially provided on said active layer through a gate insulation layer (4'). Said active layer (3') is subject to injection of P-type or N-type impurities to provide an image sensor of MOS structure. Bias potential is applied to a gate electrode so that a circuit between a source and a drain is in an On state, so that input light through said substrate or said gate electrode is applied to said active layer, and electrical output depending upon said input light is obtained from said source electrode or said drain electrode. Other MOS transistors for switching element and/or shift registers for operating said image sensor are provided on said substrate (1).Type: GrantFiled: November 22, 1994Date of Patent: November 12, 1996Assignees: TDK Corp., Semiconductor Energy Laboratory Co. Ltd.Inventors: Michio Arai, Takashi Inushima, Mitsufumi Codama, Kazushi Sugiura, Ichiro Takayama, Isamu Kobori, Yukio Yamauchi, Naoya Sakamoto
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Patent number: 5442198Abstract: A MOS-FET transistor is produced on a substrate made of glass which has a non single crystal semiconductor film (2'). The average diameter of a crystal grain in said film is in the range between 0.5 times and 4 times of thickness of said film, and said average diameter is 250 .ANG.-8000 .ANG., and said film thickness is 500 .ANG.-2000 .ANG.. The density of oxygen in the semiconductor film (2') is less than 2.times.10.sup.19 /cm.sup.3. A photo sensor having PIN structure is also produced on the substrate, to provide an image sensor for a facsimile transmitter together with the transistors. Said film (2') is produced by placing amorphous silicon film on the glass substrate through CVD process using disilane gas, and effecting solid phase growth to said amorphous silicon film by heating the substrate together with said film in nitrogen gas atmosphere. The film (2') thus produced is subject to implantation of dopant for providing a transistor.Type: GrantFiled: January 31, 1994Date of Patent: August 15, 1995Assignees: TDK Corporation, Semiconductor Energy Lab. Co., Ltd.Inventors: Michio Arai, Masaaki Ikeda, Kazushi Sugiura, Nobuo Furukawa, Mitsufumi Kodama, Yukio Yamauchi, Naoya Sakamoto, Takeshi Fukada, Masaaki Hiroki, Ichirou Takayama
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Patent number: 5432279Abstract: The present invention relates to a process for the preparation, from e.g. anhydrovinblastine, of binary indole alkaloids effective as an anti-cancer drug, such as vinblastine, leurosidine, etc., wherein a trivalent iron source and hydride source are added in the presence of oxygen, thereby increasing a yield of an object compound. The yield of an object compound is improved still more by further addition, to the reaction system, of an oxalic acid ion source, malonic acid ion source, inorganic anion source, amino acid, etc.Type: GrantFiled: May 3, 1993Date of Patent: July 11, 1995Assignee: Mitsui Petrochemical Industries, Inc.Inventors: Naoya Sakamoto, Hiroaki Tan, Eiichirou Hata, Noriaki Kihara
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Patent number: 5371285Abstract: In a method of producing a keto acid having the general formula ##STR1## wherein R.sup.1 and R.sup.2 independently represent an alkyl of 1-6 carbons or a cycloalkyl of 4-8 carbons, by reacting an m-aminophenol having the general formula ##STR2## wherein R.sup.1 and R.sup.2 are the same as above, with phthalic anhydride, in an organic solvent, the improvement comprising effecting the reaction in an amount of the organic solvent which is insufficient to dissolve the keto acid produced in the reaction, so that at least a portion of the resultant keto acid crystallizes out of the solvent and allowing the reaction to proceed in a heterogeneous system.Type: GrantFiled: March 29, 1993Date of Patent: December 6, 1994Assignee: Mitsui Petrochemical Industries, Ltd.Inventors: Masahiro Kondo, Michio Tanaka, Naoya Sakamoto, Hajime Ooyoshi