Patents by Inventor Naoyoshi Tamura

Naoyoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203854
    Abstract: A cable assembly is provided which includes a sensor body, a sensor having terminals disposed on a terminal array surface of the sensor body, and a cable holder fixed to the terminal array surface of the sensor body. The cable holder has protruding connection grooves provided at positions corresponding to the terminals of the cable holder and extending from a connection surface on the sensor side toward a cable extension surface on the opposite side. The cable assembly further includes a cable which is joined to the cable holder by soldering inner core wires to the terminals and the connection grooves.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 25, 2020
    Applicant: Molex, LLC
    Inventor: Naoyoshi TAMURA
  • Publication number: 20200014124
    Abstract: A connector is provided having a shaft member and a wire substrate. The wire substrate is wound helically on a surface of the shaft member. The wire substrate includes a band-shaped base material, a plurality of conductive wires provided on one surface of the base material, and a plurality of contact pads provided on another surface of the base material. Each of the conductive wires is connected to each of the contact pads, and the contact pads are exposed on an outside of the wire substrate aligned so as to open a gap in a length direction of the shaft member, in a state where the wire substrate is wound helically on the surface of the shaft member.
    Type: Application
    Filed: January 3, 2018
    Publication date: January 9, 2020
    Inventors: NAOYOSHI TAMURA, TAKESHI TSUKAHARA, TAKU YANAGIHASHI
  • Patent number: 10147993
    Abstract: The connecting device is composed of a first connecting member having a first housing receiving a connected first waveguide, and a second connecting member having a second housing receiving a connected second waveguide, the first housing having a first mating surface and a first magnet, and the second housing having a second mating surface and a second magnet, and the first connecting member and the second connecting member being displaced relative to each other in a mating direction orthogonal to the axial direction of the first waveguide and the second waveguide, and being positioned relative to each other by the magnetic force of the first magnet and the second magnet.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: December 4, 2018
    Assignee: Molex, LLC
    Inventors: Tomonari Nakata, Naoyoshi Tamura
  • Patent number: 9865734
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: January 9, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20170117412
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: December 13, 2016
    Publication date: April 27, 2017
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20170054194
    Abstract: The connecting device is composed of a first connecting member having a first housing receiving a connected first waveguide, and a second connecting member having a second housing receiving a connected second waveguide, the first housing having a first mating surface and a first magnet, and the second housing having a second mating surface and a second magnet, and the first connecting member and the second connecting member being displaced relative to each other in a mating direction orthogonal to the axial direction of the first waveguide and the second waveguide, and being positioned relative to each other by the magnetic force of the first magnet and the second magnet.
    Type: Application
    Filed: February 16, 2015
    Publication date: February 23, 2017
    Applicant: Molex, LLC
    Inventors: Tomonari NAKATA, Naoyoshi TAMURA
  • Patent number: 9577098
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9577309
    Abstract: To reduce electromagnetic wave transmission loss, a connecting portion is provided on the end portion of a waveguide. A connecting portion has a first half and a second half, each made of a dielectric material. An antenna formed on a printed circuit board is interposed between the first half and the second half. The connecting portion has conductive portions and. The conductive portions have a shape corresponding to the cross-section of the conductive portion of the waveguide in cross-section orthogonal to the direction in which the circuit board extends, and surround the first half and the second half.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: February 21, 2017
    Assignee: Molex, LLC
    Inventor: Naoyoshi Tamura
  • Publication number: 20160308053
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 20, 2016
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9431285
    Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 30, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
  • Patent number: 9401427
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 26, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9390960
    Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 12, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
  • Patent number: 9214524
    Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: December 15, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Naoyoshi Tamura
  • Publication number: 20150295086
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 15, 2015
    Applicant: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9112027
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 18, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20140361340
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20140333388
    Abstract: To reduce electromagnetic wave transmission loss, a connecting portion is provided on the end portion of a waveguide. A connecting portion has a first half and a second half, each made of a dielectric material. An antenna formed on a printed circuit board is interposed between the first half and the second half. The connecting portion has conductive portions and. The conductive portions have a shape corresponding to the cross-section of the conductive portion of the waveguide in cross-section orthogonal to the direction in which the circuit board extends, and surround the first half and the second half.
    Type: Application
    Filed: March 28, 2014
    Publication date: November 13, 2014
    Applicant: Molex Incorporated
    Inventor: Naoyoshi Tamura
  • Patent number: 8853673
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 8765560
    Abstract: A method of manufacturing a semiconductor device, the semiconductor device including a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8740477
    Abstract: A hybrid connector is disclosed. The hybrid connector comprises a cable, a plug and a connector housing. The cable has an optical waveguide and conductive wires disposed therein. The plug is connected to the cable. The connector housing is configured to mount on the plug. The connector housing is provided with a connector-side locking portion, an optical connection portion and an electrical connection portion.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: June 3, 2014
    Assignee: Molex Incorporated
    Inventors: Naoyoshi Tamura, Akihiro Shimotsu