Patents by Inventor Naoyoshi Tamura
Naoyoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200306508Abstract: A connector is provided that has multiple electrode rings which are arranged in a row and capable of allowing multiple wires to pass therein The connector also has a relay ring capable of allowing the multiple wires to pass therein. The relay ring has a first mating part fitted to one electrode ring of two adjacent electrode rings and a second mating part fitted to the other electrode ring.Type: ApplicationFiled: March 18, 2020Publication date: October 1, 2020Applicant: Molex, LLCInventor: Naoyoshi TAMURA
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Patent number: 10700446Abstract: A connector is provided having a shaft member and a wire substrate. The wire substrate is wound helically on a surface of the shaft member. The wire substrate includes a band-shaped base material, a plurality of conductive wires provided on one surface of the base material, and a plurality of contact pads provided on another surface of the base material. Each of the conductive wires is connected to each of the contact pads, and the contact pads are exposed on an outside of the wire substrate aligned so as to open a gap in a length direction of the shaft member, in a state where the wire substrate is wound helically on the surface of the shaft member.Type: GrantFiled: January 3, 2018Date of Patent: June 30, 2020Assignee: Molex, LLCInventors: Naoyoshi Tamura, Takeshi Tsukahara, Taku Yanagihashi
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Publication number: 20200203854Abstract: A cable assembly is provided which includes a sensor body, a sensor having terminals disposed on a terminal array surface of the sensor body, and a cable holder fixed to the terminal array surface of the sensor body. The cable holder has protruding connection grooves provided at positions corresponding to the terminals of the cable holder and extending from a connection surface on the sensor side toward a cable extension surface on the opposite side. The cable assembly further includes a cable which is joined to the cable holder by soldering inner core wires to the terminals and the connection grooves.Type: ApplicationFiled: December 12, 2019Publication date: June 25, 2020Applicant: Molex, LLCInventor: Naoyoshi TAMURA
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Publication number: 20200014124Abstract: A connector is provided having a shaft member and a wire substrate. The wire substrate is wound helically on a surface of the shaft member. The wire substrate includes a band-shaped base material, a plurality of conductive wires provided on one surface of the base material, and a plurality of contact pads provided on another surface of the base material. Each of the conductive wires is connected to each of the contact pads, and the contact pads are exposed on an outside of the wire substrate aligned so as to open a gap in a length direction of the shaft member, in a state where the wire substrate is wound helically on the surface of the shaft member.Type: ApplicationFiled: January 3, 2018Publication date: January 9, 2020Inventors: NAOYOSHI TAMURA, TAKESHI TSUKAHARA, TAKU YANAGIHASHI
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Patent number: 10147993Abstract: The connecting device is composed of a first connecting member having a first housing receiving a connected first waveguide, and a second connecting member having a second housing receiving a connected second waveguide, the first housing having a first mating surface and a first magnet, and the second housing having a second mating surface and a second magnet, and the first connecting member and the second connecting member being displaced relative to each other in a mating direction orthogonal to the axial direction of the first waveguide and the second waveguide, and being positioned relative to each other by the magnetic force of the first magnet and the second magnet.Type: GrantFiled: February 16, 2015Date of Patent: December 4, 2018Assignee: Molex, LLCInventors: Tomonari Nakata, Naoyoshi Tamura
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Patent number: 9865734Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: December 13, 2016Date of Patent: January 9, 2018Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20170117412Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: December 13, 2016Publication date: April 27, 2017Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20170054194Abstract: The connecting device is composed of a first connecting member having a first housing receiving a connected first waveguide, and a second connecting member having a second housing receiving a connected second waveguide, the first housing having a first mating surface and a first magnet, and the second housing having a second mating surface and a second magnet, and the first connecting member and the second connecting member being displaced relative to each other in a mating direction orthogonal to the axial direction of the first waveguide and the second waveguide, and being positioned relative to each other by the magnetic force of the first magnet and the second magnet.Type: ApplicationFiled: February 16, 2015Publication date: February 23, 2017Applicant: Molex, LLCInventors: Tomonari NAKATA, Naoyoshi TAMURA
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Patent number: 9577098Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: June 22, 2016Date of Patent: February 21, 2017Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9577309Abstract: To reduce electromagnetic wave transmission loss, a connecting portion is provided on the end portion of a waveguide. A connecting portion has a first half and a second half, each made of a dielectric material. An antenna formed on a printed circuit board is interposed between the first half and the second half. The connecting portion has conductive portions and. The conductive portions have a shape corresponding to the cross-section of the conductive portion of the waveguide in cross-section orthogonal to the direction in which the circuit board extends, and surround the first half and the second half.Type: GrantFiled: March 28, 2014Date of Patent: February 21, 2017Assignee: Molex, LLCInventor: Naoyoshi Tamura
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Publication number: 20160308053Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: June 22, 2016Publication date: October 20, 2016Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9431285Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.Type: GrantFiled: November 30, 2012Date of Patent: August 30, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
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Patent number: 9401427Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: June 23, 2015Date of Patent: July 26, 2016Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9390960Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.Type: GrantFiled: November 30, 2012Date of Patent: July 12, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
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Patent number: 9214524Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.Type: GrantFiled: August 15, 2012Date of Patent: December 15, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoyoshi Tamura
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Publication number: 20150295086Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: June 23, 2015Publication date: October 15, 2015Applicant: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 9112027Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: August 26, 2014Date of Patent: August 18, 2015Assignee: SOCIONEXT INC.Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20140361340Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: August 26, 2014Publication date: December 11, 2014Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20140333388Abstract: To reduce electromagnetic wave transmission loss, a connecting portion is provided on the end portion of a waveguide. A connecting portion has a first half and a second half, each made of a dielectric material. An antenna formed on a printed circuit board is interposed between the first half and the second half. The connecting portion has conductive portions and. The conductive portions have a shape corresponding to the cross-section of the conductive portion of the waveguide in cross-section orthogonal to the direction in which the circuit board extends, and surround the first half and the second half.Type: ApplicationFiled: March 28, 2014Publication date: November 13, 2014Applicant: Molex IncorporatedInventor: Naoyoshi Tamura
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Patent number: 8853673Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: May 15, 2013Date of Patent: October 7, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura