Patents by Inventor Naoyoshi Tamura
Naoyoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100320546Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.Type: ApplicationFiled: May 19, 2010Publication date: December 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Naoyoshi Tamura
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Publication number: 20100301394Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: July 29, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20100301350Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.Type: ApplicationFiled: June 29, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
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Patent number: 7821077Abstract: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.Type: GrantFiled: June 29, 2005Date of Patent: October 26, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Patent number: 7816766Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.Type: GrantFiled: May 18, 2005Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Naoyoshi Tamura, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Masashi Shima
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Patent number: 7791064Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: April 18, 2005Date of Patent: September 7, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20100178744Abstract: An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.Type: ApplicationFiled: December 23, 2009Publication date: July 15, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Haruhiko Takahashi, Hiroshi Minakata, Naoyoshi Tamura
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Publication number: 20100129971Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: ApplicationFiled: February 2, 2010Publication date: May 27, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Patent number: 7683362Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: GrantFiled: June 21, 2006Date of Patent: March 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20100047978Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.Type: ApplicationFiled: October 27, 2009Publication date: February 25, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Naoyoshi Tamura
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Patent number: 7667227Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: January 16, 2009Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20100015774Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: ApplicationFiled: September 22, 2009Publication date: January 21, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yosuke SHIMAMUNE, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Patent number: 7649232Abstract: A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film region as a compressive stress source accumulating therein a compressive stress.Type: GrantFiled: July 25, 2005Date of Patent: January 19, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Naoyoshi Tamura, Kazuo Kawamura, Akira Katakami
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Patent number: 7626215Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: GrantFiled: November 28, 2006Date of Patent: December 1, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Publication number: 20090280612Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Applicant: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090267119Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.Type: ApplicationFiled: June 30, 2009Publication date: October 29, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Naoyoshi Tamura
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Patent number: 7579617Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: GrantFiled: September 20, 2005Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090176343Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.Type: ApplicationFiled: March 3, 2009Publication date: July 9, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masashi Shima, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090134381Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of. the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: January 16, 2009Publication date: May 28, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20090114956Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.Type: ApplicationFiled: October 30, 2008Publication date: May 7, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Naoyoshi TAMURA