Patents by Inventor Naoyuki Tamura
Naoyuki Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7356798Abstract: A method including receiving, for respective terminals, wiring enable/disable information which sets a region where a connection of a wiring line is enabled and a region where a connection of a wiring line is disabled, and storing the wiring enable/disable information, and determining, using the wiring enable/disable information, whether a connection of a wiring line to a predetermined portion of a terminal of an element is enabled, and when the connection of the wiring line is enabled, executing the connection, wherein the wiring enable/disable information sets wiring enable regions at two end portions of the terminal, sets a wiring disable region at a central portion of the terminal except the two end portions, and sets an interval between either end face of the terminal and another wiring line different in longitudinal direction from the terminal to a predetermined interval not smaller than a minimum interval defined by a design rule.Type: GrantFiled: July 22, 2005Date of Patent: April 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Tamura, Takayuki Kamei
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Patent number: 7331751Abstract: A vacuum processing method includes an atmospheric transfer step of transferring a wafer in atmospheric air to a vacuum transfer chamber using atmospheric transfer equipment disposed in atmospheric air, a vacuum transfer step of transferring the wafer received from the atmospheric transfer equipment to a position for a predetermined treatment within a vacuum processing chamber using vacuum transfer equipment disposed within the vacuum transfer chamber connecting the atmospheric transfer equipment and the vacuum processing chamber, a step of detecting the displacement of the wafer in a transverse direction with respect to a traveling direction near an ingress path of the wafer to the vacuum processing chamber by comparing a correct position of the wafer passing a line which is predetermined in advance with an actual position of said wafer being transferred by the vacuum transfer equipment, and a step of correcting the detected displacement of the wafer.Type: GrantFiled: September 10, 2003Date of Patent: February 19, 2008Assignee: Hitachi High-Technologies CorporationInventor: Naoyuki Tamura
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Patent number: 7299440Abstract: According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance, causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area, and causing the arithmetic unit to lay out the standard cells in the corresponding row regions.Type: GrantFiled: November 4, 2004Date of Patent: November 20, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Yoshida, Naoyuki Tamura, You Yamamoto
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Patent number: 7290225Abstract: A method for compressing a semiconductor integrated circuit, comprising dividing a design region, in which a semiconductor integrated circuit is to be designed, into a plurality of blocks, assigning semiconductor devices to each of the blocks, determining a device density of each block, compressing any block, and connecting the blocks by wiring. In the compressing of the block, the block that is determined to have a low device density is compressed.Type: GrantFiled: October 6, 2003Date of Patent: October 30, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Naoyuki Tamura, Takayuki Kamei
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Publication number: 20060203531Abstract: A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer implemented in the graphics image space, providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern, providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns, and forming a via cell pattern.Type: ApplicationFiled: February 16, 2006Publication date: September 14, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoyuki Tamura, Yukihiro Urakawa
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Publication number: 20060184909Abstract: According to the present invention, there is provided a method of routing a semiconductor integrated circuit by using a routing apparatus having an input unit, a storage unit, and an arithmetic unit, comprising: receiving, by the input unit, for respective terminals of a plurality of elements contained in the semiconductor integrated circuit, wiring enable/disable information which sets a region where connection of a wiring line is enabled and a region where connection of a wiring line is disabled, and storing, by the storage unit, the wiring enable/disable information; and determining, by the arithmetic unit, by using the wiring enable/disable information stored in the storage unit, whether connection of a wiring line to a predetermined portion of the terminal of the element is enabled, and when the arithmetic unit determines that connection of the wiring line is enabled, execute connection.Type: ApplicationFiled: July 22, 2005Publication date: August 17, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Naoyuki Tamura, Takayuki Kamei
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Patent number: 7040639Abstract: A vehicle body structure for securing sufficient interior space and for opposing the load for forcing the suspension to fall sideward by effectively using the existing members of the body structure, thereby improving the rigidity of the vehicle body. The structure has damper bases provided at both sides of the vehicle; a cross member portion between the damper bases; and gussets fastened to both ends of the cross member portion. Each gusset is attached at the outside of an interior of the vehicle to an upper wall and a side wall of each damper base, and typically has an upper wall combined with a bottom face of the upper wall of the damper base; a side wall fastened to an outer face of the side wall of the damper base; and front and rear walls, each being joined to the upper and side walls of the gusset.Type: GrantFiled: September 3, 2003Date of Patent: May 9, 2006Assignee: Honda Giken Kogyo Kabushiki KaishaInventor: Naoyuki Tamura
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Publication number: 20050198604Abstract: According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance, causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area, and causing the arithmetic unit to lay out the standard cells in the corresponding row regions.Type: ApplicationFiled: November 4, 2004Publication date: September 8, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Yoshida, Naoyuki Tamura, You Yamamoto
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Patent number: 6899789Abstract: A method and system of holding a substrate to decrease foreign substances on the back surface thereof. The substrate holding system includes a ring-shaped leakage-proof surface having a smooth surface on the specimen table corresponding to the periphery of the substrate, contact holding portions within the periphery of the substrate, and electrostatic attraction means for fixing the substrate by contacting the back surface thereof to the ring-shaped leakage-proof surface and the contact holding portions. The substrate contacts a cooling surface at the ring-shaped leakage-proof surface and the contact holding portion placed on a position inside the ring-shaped leakage-proof surface. The back surface of the substrate and the cooling surface do not contact each other in the large portion of the remaining area.Type: GrantFiled: May 14, 2003Date of Patent: May 31, 2005Assignee: Hitachi, Ltd.Inventors: Naoyuki Tamura, Kazue Takahashi, Youichi Ito, Yoshifumi Ogawa, Hiroyuki Shichida, Tsunehiko Tsubone
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Patent number: 6875306Abstract: A vacuum processing device includes at least one vacuum processing chamber for performing predetermined treatments to a wafer being transferred to a predetermined position within the chamber, an atmospheric transfer equipment for transferring a wafer in atmospheric air to a vacuum transfer equipment which is disposed within a vacuum transfer chamber connecting the atmospheric air and the vacuum processing chambers for transferring the wafer received from the atmospheric transfer equipment to the predetermined position within the vacuum processing chamber, and wafer position sensors disposed near the ingress path leading into the processing chamber for detecting the displacement of the wafer being transferred.Type: GrantFiled: August 15, 2002Date of Patent: April 5, 2005Assignee: Hitachi High-Technologies CorporationInventor: Naoyuki Tamura
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Publication number: 20050015735Abstract: A method for compressing a semiconductor integrated circuit, comprising dividing a design region, in which a semiconductor integrated circuit is to be designed, into a plurality of blocks, assigning semiconductor devices to each of the blocks, determining a device density of each block, compressing any block, and connecting the blocks by wiring. In the compressing of the block, the block that is determined to have a low device density is compressed.Type: ApplicationFiled: October 6, 2003Publication date: January 20, 2005Inventors: Naoyuki Tamura, Takayuki Kamei
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Patent number: 6838833Abstract: A plasma processing apparatus provided with a holding stage of a system in which a temperature of an electrode block is controlled so as to control the temperature of a semiconductor wafer. The electrode block is provided with at least first and second independent temperature controllers on inner and outer sides thereof, and a slit for suppressing heat transfer is provided in the electrode block between the first and second temperature controllers.Type: GrantFiled: September 26, 2003Date of Patent: January 4, 2005Assignees: Hitachi, Ltd., Hitachi High-Technologies CorporationInventors: Masatsugu Arai, Ryujiro Udo, Naoyuki Tamura, Masanori Kadotani, Motohiko Yoshigai
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Publication number: 20040074603Abstract: The vacuum processing device comprises vacuum processing chambers 30a and 30b for performing predetermined treatments to a wafer being transferred to a predetermined position within the chamber, an atmospheric transfer equipment 7 for transferring a wafer in atmospheric air to a vacuum transfer equipment 10, a vacuum transfer equipment 10 disposed with in a vacuum transfer chamber 2 connecting the atmospheric air and said vacuum processing chambers for transferring the wafer received from said atmospheric transfer equipment to said predetermined position within said vacuum processing chamber, and wafer position sensors 11a, 11b, 11c and 11d disposed near the ingress path leading into said processing chambers for detecting the displacement of said wafers being transferred.Type: ApplicationFiled: September 10, 2003Publication date: April 22, 2004Inventor: Naoyuki Tamura
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Publication number: 20040061449Abstract: A plasma processing apparatus provided with a holding stage of a system in which a temperature of an electrode block is controlled so as to control the temperature of a semiconductor wafer. The electrode block is provided with at least first and second independent temperature controllers on inner and outer sides thereof, and a slit for suppressing heat transfer is provided in the electrode block between the first and second temperature controllers.Type: ApplicationFiled: September 26, 2003Publication date: April 1, 2004Inventors: Masatsugu Arai, Ryujiro Udo, Naoyuki Tamura, Masanori Kadotani, Motohiko Yoshigai
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Publication number: 20040051292Abstract: A vehicle body structure for securing sufficient interior space and for opposing the load for forcing the suspension to fall sideward by effectively using the existing members of the body structure, thereby improving the rigidity of the vehicle body. The structure has damper bases provided at both sides of the vehicle; a cross member portion between the damper bases; and gussets fastened to both ends of the cross member portion. Each gusset is attached at the outside of an interior of the vehicle to an upper wall and a side wall of each damper base, and typically has an upper wall combined with a bottom face of the upper wall of the damper base; a side wall fastened to an outer face of the side wall of the damper base; and front and rear walls, each being joined to the upper and side walls of the gusset.Type: ApplicationFiled: September 3, 2003Publication date: March 18, 2004Applicant: HONDA GIKEN KOGYO KABUSHIKI KAISHAInventor: Naoyuki Tamura
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Patent number: 6676805Abstract: A method and system of holding a substrate where foreign substances on the back surface can be decreased. The substrate holding system comprises a ring-shaped leakage-proof surface having a smooth surface on the specimen table corresponding to the periphery of the substrate, a plurality of contact holding portions within the periphery of the substrate, and electrostatic attraction means for fixing the substrate by contacting the back surface of the substrate to the ring-shaped leakage-proof surface and the contact holding portions. The substrate contacts to the cooling surface at the ring-shaped leakage-proof surface and the contact holding portion placed on a position inside the ring-shaped leakage-proof surface. The back surface of the substrate and the cooling surface do not contact to each other in the large portion of the remaining area.Type: GrantFiled: March 28, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Naoyuki Tamura, Kazue Takahashi, Youichi Ito, Yoshifumi Ogawa, Hiroyuki Shichida, Tsunehiko Tsubone
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Patent number: 6664738Abstract: There is provided a plasmar processing apparatus capable of positively controlling the temperature distribution of a semiconductor wafer during etching processing in a clear state, wherein an electrode block is provided with independent slits as coolant flow paths on the inner and outer peripheries and, at the same time, between these slits is formed a slit for suppressing heat transfer between the inner and outer peripheries, and owing to this slit for suppressing heat transfer, a uniform temperature in the electrode block is suppressed and thus it is possible to obtain an arbitrary independent temperature in the plane of the electrode block and positive and clear control of temperature distribution patterns can be performed.Type: GrantFiled: February 27, 2002Date of Patent: December 16, 2003Assignees: Hitachi, Ltd., Hitachi High-TechnologiesInventors: Masatsugu Arai, Ryujiro Udo, Naoyuki Tamura, Masanori Kadotani, Motohiko Yoshigai
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Patent number: 6645871Abstract: A method and system of holding a substrate where foreign substances on the back surface can be decreased. The substrate holding system comprises a ring-shaped leakage-proof surface having a smooth surface on the specimen table corresponding to the periphery of the substrate, a plurality of contact holding portions within the periphery of the substrate, and electrostatic attraction means for fixing the substrate by contacting the back surface of the substrate to the ring-shaped leakage-proof surface and the contact holding portions. The substrate contacts to the cooling surface at the ring-shaped leakage-proof surface and the contact holding portion placed on a position inside the ring-shaped leakage-proof surface. The back surface of the substrate and the cooling surface do not contact to each other in the large portion of the remaining area.Type: GrantFiled: December 21, 2001Date of Patent: November 11, 2003Assignee: Hitachi, Ltd.Inventors: Naoyuki Tamura, Kazue Takahashi, Youichi Ito, Yoshifumi Ogawa, Hiroyuki Shichida, Tsunehiko Tsubone
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Publication number: 20030197530Abstract: A semiconductor logical operation circuit comprises a logical operation part to output a result of a predetermined logical operation with respect to a plurality of input signals to an output node; a precharger to precharge said output node at a constant-potential before an operation of said logical operation part; and a setting part to forcibly set said output node at a reference potential when said logical operation part is in a non-operation state.Type: ApplicationFiled: June 14, 2002Publication date: October 23, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naoyuki Tamura
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Publication number: 20030192647Abstract: Present invention provides a method of holding substrate and a substrate holding system where the amount of foreign substances on the back surface can be decreased, and a little amount of foreign substances may be transferred from a mounting table to a substrate. The substrate holding system comprises a ring-shaped leakage-proof surface having smooth surface on the specimen table corresponding to the periphery of the substrate, a plurality of contact holding portions against the substrate on the specimen table between the corresponding position to the periphery of the substrate and the corresponding position to the center of the substrate, and electrostatic ttraction means for fixing the substrate by contacting the back surface of the substrate to the ring-shaped leakage-proof surface and the contact holding portions. The substrate contacts to the cooling surface at the ring-shaped leakage-proof surface and the contact holding portion placed on a position inside the ring-shaped leakage-proof surface.Type: ApplicationFiled: May 14, 2003Publication date: October 16, 2003Inventors: Naoyuki Tamura, Kazue Takahashi, Youichi Ito, Yoshifumi Ogawa, Hiroyuki Shichida, Tsunehiko Tsubone