Abstract: An analog to digital conversion circuit includes a first circuit (10) for receiving an analog signal (16) applied to an input (e.g., 26) of the first circuit via a connection to an analog source (e.g., 18) and generating a first residue (58) of the analog signal at an output (e.g., 32). The first circuit may be selectively configurable in a first mode for integrating the analog signal to generate an integrated analog signal and configurable in a second mode for disconnecting the first circuit from the analog source while folding the integrated analog signal to generate the first residue. The analog to digital conversion circuit also includes a second circuit (60) coupled to the output of the first circuit for resolving the first residue provided by the first circuit and for generating a further resolved second residue (98).

Abstract: A multi-channel analog to digital conversion circuit and methods thereon are provided. The multi-channel analog to digital conversion cirucit comprises a plurality of linearized channels wherein each channel comprises a multi-stage pipelined charge-to-digital converter and an integrating capacitor within each stage of the multi-stage converter wherein analog residue is processed by subsequent analog to digital converter stages. Each stage of respective linearized channels is configured for calculating gain and offset for each stage in the channel and such gain and offset is used in subsequent integration periods.

Abstract: A method for calibrating a segmented analog to digital signal conversion system is provided. The method includes segmenting a desired relationship between DAC output values and desired ADC input values into a plurality of segments. Each of the plurality of segments includes an offset value and a gain value. The method also includes computing the offset value and an offset coefficient for each of the plurality of segments, computing the gain value and an gain coefficient for each of the plurality of segments, and storing the offset value and the gain value for each of the plurality of segments in a memory unit for reference in converting an analog signal to a digital signal based upon the gain value and offset value.

Abstract: A time interval to voltage converter with very low nonlinearity for time stamping events. The converter automatically selects one of two clocks related to a reference clock and ensures that the time between an event edge to a clock edge is sufficiently large to properly operate a switch and yield very linear time-to-voltage conversion.

Abstract: A time interval to voltage converter with very low nonlinearity for time stamping events. The converter automatically selects one of two clocks related to a reference clock and ensures that the time between an event edge to a clock edge is sufficiently large to properly operate a switch and yield very linear time-to-voltage conversion.

Abstract: A method for managing clinical study (CS) information for a clinical research entity using a server system coupled to a centralized database and at least one client system is provided. The centralized database has a plurality of templates stored therein. The method includes receiving at the server system CS information relating to at least one patient involved in a clinical study wherein the CS information is entered through a user selected template displayed on the client system, storing CS information received at the server system in the centralized database, tracking CS information stored in the centralized database, updating the centralized database periodically with newly received CS information to maintain CS information, and providing CS information in response to an inquiry.

Abstract: A sensing circuit for a triac dimmable gas discharge lamp ballast uses the duty cycle of the output waveform of a conventional triac dimmer as the parameter representing a set point for controlling the degree of clamping applied to the ballast circuit, and thus the amount of light produced by a fluorescent lamp. The sensing circuit may include a comparator that receives a rectified output waveform of a triac dimmer and produces output pulses corresponding in width to the duty cycle of the waveform, and a capacitor averaging the values of the pulses produced by the comparator to produce a set point signal representing a dimming level of the lamp. A triac dimmable ballast circuit using this sensing circuit has reduced sensitivity to line voltage and a wide mechanical range over which the light level of the fluorescent lamp is controlled by the user. The sensing circuit also enables a preheat timing circuit that eliminates the timing capacitor of prior art preheating circuits.

Abstract: A sensing circuit for a triac dimmable gas discharge lamp ballast uses the duty cycle of the output waveform of a conventional triac dimmer as the parameter representing a set point for controlling the degree of clamping applied to the ballast circuit, and thus the amount of light produced by a fluorescent lamp. The sensing circuit may include a comparator that receives a rectified output waveform of a triac dimmer and produces output pulses corresponding in width to the duty cycle of the waveform, and a capacitor averaging the values of the pulses produced by the comparator to produce a set point signal representing a dimming level of the lamp. A triac dimmable ballast circuit using this sensing circuit has reduced sensitivity to line voltage and a wide mechanical range over which the light level of the fluorescent lamp is controlled by the user. The sensing circuit also enables a preheat timing circuit that eliminates the timing capacitor of prior art preheating circuits.

Abstract: An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor.