Abstract: A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

Abstract: A gravity driven Thermosiphon solar water heating system to harness solar insolation in low sunshine regions. This innovatory system uses CO2 as the working fluid to collect even mild sunlight to heat the water in sub-zero temperature areas. This solar water heater harnesses solar energy by fitting U-shaped copper heat removal pipes in evacuated glass tubes. This system works automatically by natural thermosiphon circulation force caused by density difference of supercritical CO2 at different temperatures. This innovatory solar water heater can perform in ice cold temperature areas where water based systems cease to function after freezing.

Abstract: This disclosure provides a stress-responsive polypeptide sequence for fusion with a polypeptide to specifically induce stability of the fusion polypeptide under stress conditions, such as drought, high salt and high temperature, in plants. Also disclosed includes an expression vector for expressing a fusion polypeptide comprising the stress-responsive peptide in plants transformed therewith, and a method for generating a transgenic plant with enhanced tolerance to environmental stresses, comprising introducing into the transgenic plant a polynucleotide encoding a fusion polypeptide which comprises the stress-responsive peptide as disclosed and a plant anti-stress gene, such as the plant senescence-associated gene SSPP. A plant expressing the expression vector that have an enhanced stress tolerance, including Arabidopsis and soybean, is also provided.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.

Abstract: Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

Abstract: A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

Abstract: A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Abstract: A first droop mitigation methodology in which the clock frequency applied to a processor's core is reduced from its normal operating value when a droop event capable of causing the first droop in the voltage being delivered to the core is anticipated. The reduced core switching frequency reduces the average core current, thereby mitigating the first droop. The reduced frequency is then gradually increased back to its normal operating value through a multi-step frequency ramp, instead of one fixed step. A pre-determined delay may be applied prior to each frequency increase step. A clock generator in the processor die may be configured to perform such frequency staggering in response to a droop event signal, which may be generated by the operating system or other program code being executed by the processor. The frequency staggering-based first droop mitigation may be predominantly software-based, and can be applied to core power delivery.

Abstract: An overcurrent detection circuit and method for one or more capacitive loads includes sensing current being supplied to the one or more capacitive loads to thereby generate a sensed current, and sensing a voltage rate of change across the one or more capacitive loads to thereby generate a differentiator output. The differentiator output is added to a fixed reference setpoint to thereby generate an overcurrent setpoint. The sensed current is compared to the overcurrent setpoint, and an overcurrent trip signal is supplied when the sensed current is greater than or equal to the overcurrent setpoint.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract: A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract: An overcurrent detection circuit and method for one or more capacitive loads includes sensing current being supplied to the one or more capacitive loads to thereby generate a sensed current, and sensing a voltage rate of change across the one or more capacitive loads to thereby generate a differentiator output. The differentiator output is added to a fixed reference setpoint to thereby generate an overcurrent setpoint. The sensed current is compared to the overcurrent setpoint, and an overcurrent trip signal is supplied when the sensed current is greater than or equal to the overcurrent setpoint.

Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.

Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.