Abstract: A suppression circuit may be added to a motor driver circuit, which suppresses offset voltage and ringing in the output signal. The suppression circuit may include an RC circuit filter connected to a pin of a microchip providing a gating reference signal and a junction between high and low side MOSFETS connected to the microchip.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.

Abstract: A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Abstract: A suppression circuit may be added to a motor driver circuit, which suppresses offset voltage and ringing in the output signal. The suppression circuit may include an RC circuit filter connected to a pin of a microchip providing a gating reference signal and a junction between high and low side MOSFETS connected to the microchip.

Abstract: A zwitterionic/amphiphilic pentablock copolymer was prepared using atom transfer radical polymerization (ATRP). The pentablock copolymer is prepared for the atom transfer radical polymerization of a PDMS-PEO-Br macroinitiator and SBMA. The pentablock copolymer is incorporated into a polyurethane coating composition which is useful for antifouling and/or fouling release applications.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: A zwitterionic/amphiphilic pentablock copolymer was prepared using atom transfer radical polymerization (ATRP). The pentablock copolymer is prepared for the atom transfer radical polymerization of a PDMS-PEO-Br macroinitiator and SBMA. The pentablock copolymer is incorporated into a polyurethane coating composition which is useful for antifouling and/or fouling release applications.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with the present invention may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data transmission line. The digital control loop stabilizes input/output impedance matching of various devices to within a precise ohmic range that is far narrower than standard process variations, such as sheet resistance, within the components themselves. The impedance matching circuit also overcomes EMI problems normally associated with digital control and thus provides dynamic on-chip digital control without non-linearity and with tighter tolerance than is presently possible. Accordingly, the circuit boosts performance of peripheral devices that communicate over a standard USB port, without the need for a computer as a go between or intermediate interface. This makes device to device communication possible as between USB On-the-Go capable devices.

Abstract: The invention provides a method of attenuating graft rejection in a patient undergoing an organ or tissue transplantation procedure. The inventive method involves administering FK778 using a dosing regimen that includes a period of customized administration to achieve or approximate a target whole blood trough level of FK778. The regimen optionally includes administration of a calcineurin inhibitor, such as Tacrolimus, and/or a steroid, and/or an antiviral. Specific preferred quantities of these pharmaceutically-active agents are provided as well as preferred timing and routes of administration. The invention also provides a medical kit for administering FK778. The kit includes printed instructions for administering FK778 to the patient undergoing a graft transplantation procedure according to a dosing regimen containing a period during which the dosage of FK778 is adjusted to deliver an amount of FK778 sufficient to maintain a target whole blood though level of FK778, such as described herein.