Patents by Inventor Nasrullah

Nasrullah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8861145
    Abstract: A suppression circuit may be added to a motor driver circuit, which suppresses offset voltage and ringing in the output signal. The suppression circuit may include an RC circuit filter connected to a pin of a microchip providing a gating reference signal and a junction between high and low side MOSFETS connected to the microchip.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 14, 2014
    Assignee: Honeywell International Inc.
    Inventors: Joseph Marotta, Dale Trumbo, Nasrullah Habeeb M, Rajamohan Revindranathan
  • Publication number: 20140281602
    Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: David Pardo Keppel, Jawad Nasrullah
  • Publication number: 20140281254
    Abstract: A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Christopher WILKERSON, Jawad NASRULLAH, Kelvin KWAN
  • Publication number: 20140189401
    Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: DAVID PARDO KEPPEL, JAWAD JAKE NASRULLAH
  • Publication number: 20140189240
    Abstract: A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
    Type: Application
    Filed: December 29, 2012
    Publication date: July 3, 2014
    Inventors: David KEPPEL, Kelvin KWAN, Jawad NASRULLAH
  • Publication number: 20140022676
    Abstract: A suppression circuit may be added to a motor driver circuit, which suppresses offset voltage and ringing in the output signal. The suppression circuit may include an RC circuit filter connected to a pin of a microchip providing a gating reference signal and a junction between high and low side MOSFETS connected to the microchip.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 23, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: JOSEPH MAROTTA, DALE TRUMBO, NASRULLAH HABEEB M, RAJAMOHAN REVINDRANATHAN
  • Patent number: 8629210
    Abstract: A zwitterionic/amphiphilic pentablock copolymer was prepared using atom transfer radical polymerization (ATRP). The pentablock copolymer is prepared for the atom transfer radical polymerization of a PDMS-PEO-Br macroinitiator and SBMA. The pentablock copolymer is incorporated into a polyurethane coating composition which is useful for antifouling and/or fouling release applications.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: January 14, 2014
    Assignee: NDSU Research Foundation
    Inventors: Dean C. Webster, Robert J. Pieper, Mohammed J. Nasrullah
  • Patent number: 8298896
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 30, 2012
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Publication number: 20120166838
    Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Inventors: Jawad Nasrullah, Kelvin Kwan, David Roger Ditzel, Vjekoslav Svilan
  • Publication number: 20120151235
    Abstract: Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 14, 2012
    Inventors: Jawad Nasrullah, Kelvin Kwan, Jaydeep P. Kulkarni, Muhammad M. Khellah
  • Publication number: 20110300681
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Publication number: 20110218290
    Abstract: A zwitterionic/amphiphilic pentablock copolymer was prepared using atom transfer radical polymerization (ATRP). The pentablock copolymer is prepared for the atom transfer radical polymerization of a PDMS-PEO-Br macroinitiator and SBMA. The pentablock copolymer is incorporated into a polyurethane coating composition which is useful for antifouling and/or fouling release applications.
    Type: Application
    Filed: October 9, 2009
    Publication date: September 8, 2011
    Applicant: NDSU RESEARCH FOUNDATION
    Inventors: Dean C. Webster, Robert J. Pieper, Mohammed J. Nasrullah
  • Patent number: 8003471
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: August 23, 2011
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Publication number: 20100159662
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Application
    Filed: March 1, 2010
    Publication date: June 24, 2010
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Patent number: 7683442
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with the present invention may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 23, 2010
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Patent number: 7068065
    Abstract: An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data transmission line. The digital control loop stabilizes input/output impedance matching of various devices to within a precise ohmic range that is far narrower than standard process variations, such as sheet resistance, within the components themselves. The impedance matching circuit also overcomes EMI problems normally associated with digital control and thus provides dynamic on-chip digital control without non-linearity and with tighter tolerance than is presently possible. Accordingly, the circuit boosts performance of peripheral devices that communicate over a standard USB port, without the need for a computer as a go between or intermediate interface. This makes device to device communication possible as between USB On-the-Go capable devices.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: June 27, 2006
    Assignee: Innovative Semiconductors
    Inventor: Jawad Nasrullah
  • Publication number: 20060063794
    Abstract: The invention provides a method of attenuating graft rejection in a patient undergoing an organ or tissue transplantation procedure. The inventive method involves administering FK778 using a dosing regimen that includes a period of customized administration to achieve or approximate a target whole blood trough level of FK778. The regimen optionally includes administration of a calcineurin inhibitor, such as Tacrolimus, and/or a steroid, and/or an antiviral. Specific preferred quantities of these pharmaceutically-active agents are provided as well as preferred timing and routes of administration. The invention also provides a medical kit for administering FK778. The kit includes printed instructions for administering FK778 to the patient undergoing a graft transplantation procedure according to a dosing regimen containing a period during which the dosage of FK778 is adjusted to deliver an amount of FK778 sufficient to maintain a target whole blood though level of FK778, such as described herein.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Applicant: Fujisawa Pharmaceutical Co., Ltd.
    Inventors: Karsten Roth, Nasrullah Undre
  • Patent number: D706961
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Nasrullah, Eko Yulianto