Patents by Inventor Nasser A. Kurd

Nasser A. Kurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210181831
    Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 17, 2021
    Applicant: Intel Corporation
    Inventors: Praveen MOSALIKANTI, Nasser A. KURD, Alexander GENDLER
  • Publication number: 20210082481
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Publication number: 20210083678
    Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
    Type: Application
    Filed: September 22, 2020
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
  • Publication number: 20210055921
    Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Intel Corporation
    Inventors: Julien Sebot, Edward A. Burton, Nasser A. Kurd, Jonathan Douglas
  • Patent number: 10928886
    Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Alexander Gendler
  • Publication number: 20210049307
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
  • Patent number: 10854249
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10824764
    Abstract: An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Nasser Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark Neidengard, Vaughn Grossnickle, Qi S. Wang, Kandadai Ramesh
  • Publication number: 20200327914
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: June 27, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10790832
    Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
  • Patent number: 10790838
    Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Vaughn J. Grossnickle, Syed Feruz Syed Farooq, Mark Neidengard, Nasser A. Kurd
  • Publication number: 20200285267
    Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Mohamed A. Abdelmoneum, Nasser A. Kurd, Thripthi Hegde
  • Publication number: 20200272197
    Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.
    Type: Application
    Filed: September 6, 2018
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Publication number: 20200272220
    Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Inventors: Praveen MOSALIKANTI, Nasser KURD, Alexander GENDLER
  • Patent number: 10706900
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10707877
    Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Turbo Majumder, Minki Cho, Carlos Tokunaga, Praveen Mosalikanti, Nasser A. Kurd, Muhammad M. Khellah
  • Patent number: 10707878
    Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum
  • Patent number: 10686582
    Abstract: An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Gerald Pasdast, Nasser A. Kurd, Peipei Wang, Yingyu Miao, Lakshmipriya Seshan, Ishaan S. Shah
  • Publication number: 20200143853
    Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Navindra Navaratnam, Nasser A. Kurd, Bee Min Teng, Raymond Chong, Nasirul I. Chowdhury, Ali M. El-Husseini
  • Patent number: 10614774
    Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Nasser Kurd, Daniel Ragland, Ameya Ambardekar, John Fallin, Praveen Mosalikanti, Vaughn J. Grossnickle