Patents by Inventor Nasser A. Kurd

Nasser A. Kurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140254734
    Abstract: Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Inventors: Mohamed A. Abdelmoneum, Nasser A. Kurd, Amr M. Lotfy, Mamdouh O. Abd El-Mejeed, Mohamed A. Abdelsalam
  • Publication number: 20140218088
    Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.
    Type: Application
    Filed: December 15, 2011
    Publication date: August 7, 2014
    Inventors: Mark Neidengaed, Vaughn Grossnickle, Nasser Kurd, Jeffrey Krieger
  • Patent number: 8756451
    Abstract: Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: June 17, 2014
    Assignee: Intel Corporation
    Inventors: Mark L. Neidengard, Nasser A. Kurd, Robert J. Greiner, Vaughn J. Grossnickle
  • Patent number: 8736328
    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Thomas P. Thomas
  • Publication number: 20140103973
    Abstract: Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.
    Type: Application
    Filed: December 20, 2011
    Publication date: April 17, 2014
    Inventors: Nasser A. Kurd, Vaughn J. Grossnickle
  • Publication number: 20130307631
    Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.
    Type: Application
    Filed: March 22, 2012
    Publication date: November 21, 2013
    Inventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum
  • Publication number: 20130300475
    Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.
    Type: Application
    Filed: December 22, 2011
    Publication date: November 14, 2013
    Inventors: Nasser A. Kurd, Thomas P. Thomas
  • Patent number: 8552781
    Abstract: Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Patent number: 8502612
    Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Timothy M. Wilson
  • Publication number: 20130086410
    Abstract: Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.
    Type: Application
    Filed: October 1, 2011
    Publication date: April 4, 2013
    Inventors: Nasser A. Kurd, Robert J. Greiner, Mark L. Neidengard, Vaughn J. Grossnickle
  • Patent number: 8350610
    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Harishankar Sridharan, Jacob Schneider, Pushkar Gorur, Nasser A. Kurd
  • Patent number: 8258837
    Abstract: Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Patent number: 8248124
    Abstract: A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Christopher P. Mozak
  • Publication number: 20120019285
    Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: Intel Corporation
    Inventors: Praveen Mosalikanti, Harishankar Sridharan, Jacob Schneider, Pushkar Gorur, Nasser A. Kurd
  • Publication number: 20110298501
    Abstract: A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 8, 2011
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Christopher P. Mozak
  • Publication number: 20110285469
    Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Timothy M. Wilson
  • Patent number: 8031017
    Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser A. Kurd, Timothy M. Wilson
  • Publication number: 20110148486
    Abstract: Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Publication number: 20110148498
    Abstract: Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Patent number: 7873134
    Abstract: Disclosed herein are clock generator systems comprising first and second stage PLLs thereby allowing for both lower PLL bandwidth filtering and higher bandwidth response, in accordance with some embodiments. Other systems may be disclosed and/or described herein.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 18, 2011
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Ravindra B. Venigalla