Abstract: In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit.

Abstract: A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

Abstract: In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit. Several embodiments are disclosed. In a first embodiment, a glitch protection circuit generates an output that represents a logical multiplication of a strobe signal with a delayed version of itself. In another embodiment, a pair of glitch protection circuits each sense a strobe transition and become dormant until its partner senses a strobe transition. The pair operates in a toggling fashion.

Abstract: A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

Abstract: In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.

Abstract: Various apparatuses and methods to generate a clock signal that controls data operations in an integrated circuit. In an embodiment, a circuit for generating a clock signal that controls data operations in an integrated circuit includes a first clock synthesizer, a divider circuit, and a second clock synthesizer. The first clock synthesizer produces a first signal derived from an external reference signal. The first signal has a first frequency that is greater than a frequency of the external reference signal. The divider circuit divides the frequency of the first signal by N, where N is an integer greater than 1. The divider circuit outputs a second signal having a second frequency which is equal to the first frequency divided by N. The second clock synthesizer couples to the divider circuit for producing the clock signal at a frequency which is an integer multiple of the second signal. The second clock synthesizer also produces a strobe signal.

Abstract: An integrated circuit includes a first circuit, a second circuit, at least one test pad and multiplexing circuitry. The second circuit is coupled to the first circuit and has substantially the same design as the first circuit to emulate an electrical characteristic of the first circuit. The multiplexing circuitry selectively couples the test pad(s) to the second circuit to selectively measure the electrical characteristic.

Abstract: A method and apparatus for skew measure and dynamic skew and jitter error compensation. A plurality of programmable delay lines corresponding to a plurality of signals is provided, wherein each delay line is in a path of a corresponding signal. A skew measure circuit is configured to receive at least two signals to be synchronized. The skew measure circuit determines a phase difference between the at least two signals. The skew measure circuit is coupled to the programmable delay lines and uses the phase difference to program at least one of the delay lines to delay at least one of the signals to be synchronized such that the signals are in synchronization.

Abstract: A phase lock loop system is provided that includes a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal. The phase lock loop system may include a width control circuit to alter a width of the first control signal and to produce an altered first control signal.

Abstract: According to one embodiment, a clock enable generator circuit comprises a decode module configured to generate enable pulses. The decode module generates the enable pulses in response to receiving a clock ratio signal. The clock enable generator circuit further includes a first and second output circuit. The first output circuit is coupled to the decode module and is configured to generate a first set of clock enables in response to receiving an enable pulse from the decode module. The second output circuit is coupled to the decode module and is configured to generate a second set of clock enables. The clock enable generator circuit is configured to generate different sets of clock enables for each of a plurality of clock ratio signals. According to a further embodiment, The clock enable generator circuit further comprises a third output circuit coupled to the decode module. The first output circuit generates the first set of clock enables in response to the decode module receiving an even ratio signal.

Abstract: A sense amplifier comprising first and second CMOS inverters, an pMOS current mirror, a nMOS current mirror, a source pMOSFET to source current, and a sink nMOSFET to sink current. The gate voltage of the first CMOS inverter is the input voltage and the gate voltage of the second CMOS inverter is at the reference voltage. The output voltage is at the drains of the first CMOS inverter. The pMOS and nMOS current mirrors provide active loads to the first and second CMOS inverters. The sense amplifier is self-biasing by connecting the gate of the source pMOSFET to the gates of the pMOS current mirror and by connecting the gate of the sink nMOSFET to the gates of the nMOS current mirror.

Abstract: A circuit including a configurable mode device configured to generate an output signal in response to a differential control signal, the differential control signal representing a phase difference between at least two signals. Additionally, a state machine configured to generate a control signal in response to a mode selection signal, wherein the control signal configures the configurable mode device to operate in either a delay lock loop mode or a phase lock loop mode.