Patents by Inventor Navas Khan Oratti Kalandar
Navas Khan Oratti Kalandar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11152321Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.Type: GrantFiled: February 7, 2020Date of Patent: October 19, 2021Assignees: Infineon Technologies AG, Infineon Technologies Americas Corp.Inventors: Carlo Marbella, Swee Guan Chan, Eung San Cho, Navas Khan Oratti Kalandar
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Publication number: 20200258855Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.Type: ApplicationFiled: February 7, 2020Publication date: August 13, 2020Inventors: Carlo Marbella, Swee Guan Chan, Eung San Cho, Navas Khan Oratti Kalandar
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Patent number: 10431534Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.Type: GrantFiled: January 8, 2018Date of Patent: October 1, 2019Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
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Publication number: 20190181079Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.Type: ApplicationFiled: January 8, 2018Publication date: June 13, 2019Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
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Publication number: 20190157222Abstract: Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.Type: ApplicationFiled: November 20, 2017Publication date: May 23, 2019Inventors: Nishant LAKHERA, Andrew Jefferson MAWER, Akhilesh Kumar SINGH, Navas Khan ORATTI KALANDAR
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Publication number: 20190103365Abstract: Embodiments for a packaged semiconductor device are provided herein, which includes a substrate; an antenna module attached to a top surface of the substrate, the antenna module including an antenna; an electronic component attached to the top surface of the substrate, the electronic component communicatively coupled to the antenna module through electrical connections in the substrate; a first portion of mold body that encapsulates the antenna module; a second portion of mold body that encapsulates the electronic component, wherein the second portion of mold body is separated from the first portion of mold body by at least a first trench; and a shielding layer that covers the second portion of mold body.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Akhilesh Kumar SINGH, Nishant Lakhera, Navas Khan Oratti Kalandar
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Patent number: 10211184Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: GrantFiled: November 3, 2017Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, Navas Khan Oratti Kalandar, Akhilesh K. Singh
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Patent number: 10147645Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.Type: GrantFiled: September 22, 2015Date of Patent: December 4, 2018Assignee: NXP USA, Inc.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
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Patent number: 9997445Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.Type: GrantFiled: December 15, 2016Date of Patent: June 12, 2018Assignee: NXP USA, INC.Inventors: Kai Yun Yow, Chee Seng Foong, Bihua He, Navas Khan Oratti Kalandar, Lan Chu Tan, Yuan Zang
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Publication number: 20180114748Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.Type: ApplicationFiled: December 15, 2016Publication date: April 26, 2018Inventors: Kai Yun Yow, Chee Seng Foong, Bihua He, Navas Khan Oratti Kalandar, Lan Chu Tan, Yuan Zang
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Publication number: 20180114745Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.Type: ApplicationFiled: October 25, 2016Publication date: April 26, 2018Inventors: NAVAS KHAN ORATTI KALANDAR, AKHILESH KUMAR SINGH, NISHANT LAKHERA
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Patent number: 9953904Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.Type: GrantFiled: October 25, 2016Date of Patent: April 24, 2018Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Akhilesh Kumar Singh, Nishant Lakhera
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Patent number: 9947614Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.Type: GrantFiled: March 9, 2016Date of Patent: April 17, 2018Assignee: NXP USA, Inc.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Boon Yew Low, Akhilesh Singh
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Publication number: 20180053753Abstract: A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a substrate, and encapsulating the first surface of the substrate and the plurality of interconnect balls with an encapsulant. A trench is formed in a first surface of the encapsulant exposing a portion the interconnect balls. An interposer is provided having a first interconnect layer. An assembly is formed by attaching connection sites of a first interconnect layer to the exposed portion of the interconnect balls, the first surface of the second substrate extending into the trench.Type: ApplicationFiled: August 16, 2016Publication date: February 22, 2018Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Navas Khan Oratti Kalandar
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Publication number: 20180053749Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Nishant LAKHERA, Navas Khan Oratti KALANDAR, Akhilesh K. SINGH
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Publication number: 20170278825Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Inventors: Nishant LAKHERA, Navas Khan ORATTI KALANDAR, Akhilesh K. SINGH
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Publication number: 20170263538Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Navas Khan ORATTI KALANDAR, Nishant LAKHERA, Boon Yew LOW, Akhilesh SINGH
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Patent number: 9721928Abstract: A packaged IC device in which a die is sandwiched between first and second substrates such that (i) peripheral electrical contact pads of the die are wire bonded to the first substrate, e.g., for routing functional input/output signals, and (ii) core-area electrical contact pads of the die are connected to the second substrate in a flip-chip arrangement, e.g., for routing one or more power supply voltages to the core area of the die. The second substrate has a shape and position that (i) expose the peripheral electrical contact pads of the die for unencumbered machine-implemented wire bonding during the assembly process, and (ii) enable direct electrical connections between the first and second substrates outside the footprint of the die, e.g., by way of the corresponding solder bumps attached between the two substrates.Type: GrantFiled: April 28, 2016Date of Patent: August 1, 2017Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Lan Chu Tan, Chetan Verma
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Patent number: 9691637Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.Type: GrantFiled: October 7, 2015Date of Patent: June 27, 2017Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
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Publication number: 20170103905Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.Type: ApplicationFiled: October 7, 2015Publication date: April 13, 2017Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH