Abstract: A method for assembling a 3D integrated circuit package that includes a base device and a top device. The method includes bonding (i) a pre-formed via array having a via rack and via elements and (ii) a base die to the substrate of the base device. The resulting sub-assembly is encapsulated in molding compound, and the via rack and any corresponding molding compound are removed, such as by grinding, to generate a base device with vias corresponding to the via elements and exposed bond posts on its top surface corresponding to the tops of the vias. A pre-packaged or unpackaged top device is then attached and bonded to the base device and, if necessary, encapsulated to form the 3D package with the exposed tops of the vias providing electrical connections between the base substrate and the top device.

Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: A semiconductor sensor die grid array package includes a semiconductor die having an active surface and an opposite backside surface. The active surface has external die connection pads. Conductive runners respectively connect the die connection pads to external connection mounts of the package. An encapsulant covers the semiconductor die. The encapsulant has a base surface proximal to the conductive runners and a stacking surface opposite the base surface. A sensor die is supported on the stacking surface. The sensor die has an active surface and an opposite backside surface that faces the stacking surface, and the sensor active surface has sensor connection pads. Conductive vias engage with the conductive runners and also are wire bonded to one of the sensor connection pads.

Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Abstract: A semiconductor sensor device is assembled using a pre-molded lead frame having first and second die flags. The first die flag includes a cavity. A pressure sensor die (P-cell) is mounted within the cavity and a master control unit die (MCU) is mounted to the second flag. The P-cell and MCU are electrically connected to leads of the lead frame with bond wires. The die attach and wire bonding steps are each done in a single pass. A mold pin is placed over the P-cell and then the MCU is encapsulated with a mold compound. The mold pin is removed leaving a recess that is next filled with a gel material. Finally a lid is placed over the P-cell and gel material. The lid includes a hole that that exposes the gel-covered active region of the pressure sensor die to ambient atmospheric pressure outside the sensor device.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.

Abstract: A semiconductor device includes a die pad and a semiconductor die having a mounting surface attached to the die pad and an opposite, active surface with die external terminals. The device has package external connectors, each having a bond region selectively electrically coupled to the die external terminals with a bond wire. A heat spreader has a first region that encloses an inner recessed region. A thermally conductive sheet is sandwiched between the inner recessed region of the heat spreader and the active surface of the die. At least the die, die external terminals, and the bond region are covered with an encapsulant.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

Abstract: A method of making an electrical connection includes passing a bond wire through a wire bonding system having a wire polisher and a wire bonding tool. The wire polisher removes contamination from a first portion of the bond wire. A first bond is then formed by bonding the first portion of the bond wire to a first contact such that the bond wire and the first device are electrically connected. A second bond is then formed by bonding a second portion of the bond wire to a second contact such that the first contact and the second contact are electrically connected.

Abstract: A surface mount semiconductor device having external contact elements exposed in a ball grid array (BGA) at its external active face for mechanical and electrical connection to an external support and a semiconductor die connected electrically internally with the external contact elements. A reinforcement layer of electrically insulating material extends between and surrounds laterally peripheral contact elements of the BGA. The reinforcement layer extends to from about thirty percent (30%) to about fifty percent (50%) of the height of the peripheral contact elements at the active face.

Abstract: A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A semiconductor device includes first and second flexible substrates each with first and second peripheral edges. First and second dies are attached on respective surfaces of the flexible substrates and are each respectively electrically connected to first and second metal traces. A first crimping structure electrically connects the first metal traces to the second metal traces and crimps together the first peripheral edges of the first and second substrates. A second crimping structure electrically connects the first metal traces to the second metal traces and crimps together the second peripheral edges of the first and second substrates.

Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.

Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.