Patents by Inventor Navas Khan Oratti Kalandar
Navas Khan Oratti Kalandar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170084491Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH
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Patent number: 9508632Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.Type: GrantFiled: June 24, 2015Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Varughese Mathew, Akhilesh K. Singh
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Patent number: 9476788Abstract: A pressure sensor has a housing having a bottom surface and side walls that form a cavity. A pressure sensor die is attached to the bottom of the cavity and covered with a layer of low modulus gel. A lid is secured to upper ends of the side walls and covers the cavity, gel and pressure sensor die. The lid has an inner surface facing the gel and an exposed outer surface, and includes protrusions extending from the inner surface along the side walls and towards the gel such that the gel near the upper ends of the side walls is displaced towards a central region of the cavity to ensure that the gel completely covers the pressure sensor die.Type: GrantFiled: April 22, 2014Date of Patent: October 25, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Navas Khan Oratti Kalandar, Charles Bergere
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Patent number: 9401345Abstract: A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.Type: GrantFiled: September 1, 2014Date of Patent: July 26, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20160163671Abstract: A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.Type: ApplicationFiled: December 3, 2014Publication date: June 9, 2016Applicant: Freescale Semiconductor, Inc.Inventors: SHAILESH KUMAR, Rishi Bhooshan, Chee Seng Foong, Vikas Garg, Navas Khan Oratti Kalandar, Chetan Verma
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Patent number: 9299675Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.Type: GrantFiled: April 16, 2015Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR,INC.Inventors: Navas Khan Oratti Kalandar, Boon Yew Low, Kesvakumar V. C. Muniandy
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Publication number: 20160086880Abstract: A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Navas Khan Oratti Kalandar, Wai Yew Lo, Wen Shi Koh
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Publication number: 20160064356Abstract: A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.Type: ApplicationFiled: September 1, 2014Publication date: March 3, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20160056094Abstract: A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls.Type: ApplicationFiled: August 19, 2014Publication date: February 25, 2016Applicant: Freescale Semiconductor, Inc.Inventors: KESVAKUMAR V.C. MUNIANDY, Navas Khan Oratti Kalandar
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Publication number: 20150364439Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Shailesh Kumar, Rishi Bhooshan, Vikas Garg, Chetan Verma, Navas Khan Oratti Kalandar
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Patent number: 9209147Abstract: A method of forming a pillar bump includes feeding a bond wire in a capillary. The capillary has a hole portion and a chamfer section arranged downstream of the hole portion. The hole portion has a length along a feed direction of the bond wire that is greater than a maximum diameter of the hole portion. The method further includes performing an electric flame off (EFO) on a free end of the bond wire extending from the chamfer section to form a free air ball (FAB), tensioning the bond wire and applying a vacuum to the capillary to withdraw a portion of the FAB back into the capillary to substantially fill the hole portion for forming a tower, attaching the FAB to a bonding site, and at least partially removing the capillary from the bonding site and breaking the bond wire above the tower.Type: GrantFiled: July 17, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Lee Fee Ngion, Navas Khan Oratti Kalandar, Zi Song Poh
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Patent number: 9196598Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.Type: GrantFiled: June 12, 2014Date of Patent: November 24, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Shailesh Kumar, Rishi Bhooshan, Vikas Garg, Chetan Verma, Navas Khan Oratti Kalandar
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Patent number: 9190355Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.Type: GrantFiled: April 18, 2014Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150303137Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.Type: ApplicationFiled: April 18, 2014Publication date: October 22, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150300905Abstract: A pressure sensor has a housing having a bottom surface and side walls that form a cavity. A pressure sensor die is attached to the bottom of the cavity and covered with a layer of low modulus gel. A lid is secured to upper ends of the side walls and covers the cavity, gel and pressure sensor die. The lid has an inner surface facing the gel and an exposed outer surface, and includes protrusions extending from the inner surface along the side walls and towards the gel such that the gel near the upper ends of the side walls is displaced towards a central region of the cavity to ensure that the gel completely covers the pressure sensor die.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Navas Khan Oratti Kalandar, Charles Bergere
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Patent number: 9159682Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.Type: GrantFiled: September 8, 2013Date of Patent: October 13, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150243621Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.Type: ApplicationFiled: April 16, 2015Publication date: August 27, 2015Inventors: NAVAS KHAN ORATTI KALANDAR, Boon Yew Low, Kesvakumar V.C. Muniandy
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Publication number: 20150221592Abstract: A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Inventors: Chetan Verma, Rishi Bhooshan, Vikas Garg, Shailesh Kumar, Navas Khan Oratti Kalandar
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Publication number: 20150206769Abstract: A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die. The expanded die is mounted on a lead frame having conductive leads, and the conductive leads are electrically coupled to the conductive member, which acts as a power bar, and to the die bonding pads. The conductive member also is electrically coupled to at least one of the die bonding pads. The expanded die and portions of the conductive leads are encapsulated with a second encapsulant.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Inventors: Kesvakumar V.C. Muniandy, Dominic Koey, Navas Khan Oratti Kalandar
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Publication number: 20150187728Abstract: In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Kesvakumar V.C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan