Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.

Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.

Abstract: According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Abstract: A die package and a method for manufacturing the die package are provided.

Abstract: An electronic package (200) comprises a substrate (201), a first carrier layer arrangement (211) adapted to dissipate heat from at least one chip (217) mounted thereon, and a heat exchanger (221) mounted on the first carrier layer arrangement. The first carrier layer arrangement comprises at least one internal microchannel (213), which is fluidically interconnected with the heat exchanger (221) though an inlet (215) and an outlet (219). The heat exchange further comprises a pump (223) controlling fluid flow through the microchannel (213). The package may further comprise a stack of carrier layer arrangements (211), each of which may have one or more chips (217) mounted thereon.