Patents by Inventor Nazila HARATIPOUR

Nazila HARATIPOUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063131
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Publication number: 20210111179
    Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Nazila HARATIPOUR, Uygar E. AVCI
  • Publication number: 20200411686
    Abstract: A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, I-cheng Tung, Abhishek A. Sharma, Arnab Sen Gupta, Van Le, Matthew V. Metz, Jack Kavalieros, Tahir Ghani
  • Publication number: 20200411692
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
  • Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20200395435
    Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: NAZILA HARATIPOUR, CHIA-CHING LIN, SOU-CHI CHANG, IAN A. YOUNG, UYGAR E. AVCI, JACK T. KAVALIEROS
  • Publication number: 20200395460
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20200312950
    Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200312949
    Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200286687
    Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Nazila Haratipour, Seung Hoon Sung, Ashish Verma Penumatcha, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286685
    Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286686
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200105892
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Nazila HARATIPOUR, Tahir GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Benjamin CHU-KUNG, Seung Hoon SUNG, Van H. LE, Shriram SHIVARAMAN, Abhishek SHARMA
  • Publication number: 20200098934
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, where the channel layer includes a first region and a second region, and the first region has a first dopant concentration. A gate electrode is above the first region of the channel layer and separated from the channel layer by a gate dielectric layer. A spacer is next to the gate electrode to separate the gate electrode from a drain electrode or a source electrode above the channel layer. The spacer includes a dopant material in contact with the second region of the channel layer, and the second region has a second dopant concentration different from the first dopant concentration in the first region. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Shriram SHIVARAMAN, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Seung Hoon SUNG, Nazila HARATIPOUR, Abhishek SHARMA
  • Publication number: 20200098930
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
  • Publication number: 20200098931
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Abhishek SHARMA, Nazila HARATIPOUR, Seung Hoon SUNG, Benjamin CHU-KUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Matthew V. METZ, Arnab SEN GUPTA
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Publication number: 20200098887
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Jack T. KAVALIEROS, Sean MA, Seung Hoon SUNG, Nazila HARATIPOUR, Tahir GHANI, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200006572
    Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Abhishek A. SHARMA, Yih WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Benjamin CHU-KUNG, Seung Hoon SUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Matthew V. METZ