Patents by Inventor Nicholas C. M. Fuller
Nicholas C. M. Fuller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160233335Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.Type: ApplicationFiled: February 5, 2015Publication date: August 11, 2016Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C.M. Fuller, Masahiro Nakamura, Richard S. Wise
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Patent number: 9405582Abstract: Dynamically adjusting the parameters of a parallel, distributed job in response to changes to the status of the job cluster. Includes beginning execution of a job in a cluster, receiving cluster status information, determining a job performance impact of the cluster status, reconfiguring job parameters based on the performance impact, and continuing execution of the job using the updated configuration. Dynamically requesting a change to the resources of the job cluster for a parallel, distributed job in response to changes in job status. Includes beginning execution of a job in a cluster, receiving job status information, determining a job performance impact, requesting a changed allocation of cluster resources based on the determined job performance impact, reconfiguring one or more job parameters based on the changed allocation, and continuing execution of the job using the updated configuration.Type: GrantFiled: June 20, 2014Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Vijay K. Naik, Liangzhao Zeng, Li Zhang
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Publication number: 20160125172Abstract: A processor stores information associated with one or more programming modules, including one or more license terms associated with the one or more programming modules. The processor receives an input indicating a set of programming modules selected from the one or more programming modules, based on the information which is stored. The processor compares the one or more license terms associated with the set of programming modules. In response to determining a conflict between the one or more license terms of the set of programming modules, the processor applies a set of rules to resolve the conflict between the one or more license terms of the set of programming modules, and the processor composes a composite license for the set of programming modules, based on the one or more license terms of the set of programming modules and the set of rules applied to resolve the conflict.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Nicholas C. M. Fuller, Jim A. Laredo, Hui Lei, Sriram K. Rajagopal, Maja Vukovic, Liangzhao Zeng
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Publication number: 20160111374Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.Type: ApplicationFiled: October 20, 2015Publication date: April 21, 2016Inventors: Markus Brink, Robert L. Bruce, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura
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Patent number: 9263393Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: GrantFiled: May 14, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Cyril Cabral, Jr., Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Publication number: 20160026968Abstract: Automatically associating information technology resource patterns with specific information technology products by receiving a set of data about information technology assets, matching a subset of that data to a pattern in a set of patterns, determining that the subset of the data represents a product associated with that pattern, reporting this determination; receiving feedback on the accuracy of the determination, and updating pattern set information in response to that feedback.Type: ApplicationFiled: July 24, 2014Publication date: January 28, 2016Inventors: Liya Fan, Nicholas C. M. Fuller, Jian Qiu, Zhe Zhang
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Publication number: 20150370603Abstract: Dynamically adjusting the parameters of a parallel, distributed job in response to changes to the status of the job cluster. Includes beginning execution of a job in a cluster, receiving cluster status information, determining a job performance impact of the cluster status, reconfiguring job parameters based on the performance impact, and continuing execution of the job using the updated configuration. Dynamically requesting a change to the resources of the job cluster for a parallel, distributed job in response to changes in job status. Includes beginning execution of a job in a cluster, receiving job status information, determining a job performance impact, requesting a changed allocation of cluster resources based on the determined job performance impact, reconfiguring one or more job parameters based on the changed allocation, and continuing execution of the job using the updated configuration.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Nicholas C. M. Fuller, Vijay K. Naik, Liangzhao Zeng, Li Zhang
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Patent number: 9190316Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.Type: GrantFiled: October 26, 2011Date of Patent: November 17, 2015Assignees: GLOBALFOUNDRIES U.S. 2 LLC, ZEON CORPORATIONInventors: Markus Brink, Robert L. Bruce, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura
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Publication number: 20150243602Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: ApplicationFiled: May 14, 2015Publication date: August 27, 2015Inventors: Cyril Cabral, JR., Benjamin L. Fletcher, Nicholas C.M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Patent number: 9064727Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: GrantFiled: August 20, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
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Patent number: 9018090Abstract: Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.Type: GrantFiled: October 10, 2011Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Eric A. Joseph, Adam M. Pyzyna
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Patent number: 8928124Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.Type: GrantFiled: August 13, 2013Date of Patent: January 6, 2015Assignees: International Business Machines Corporation, ZEON CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura
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Patent number: 8916054Abstract: A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.Type: GrantFiled: October 26, 2011Date of Patent: December 23, 2014Assignees: International Business Machines Corporation, Zeon CorporationInventors: Markus Brink, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Hiroyuki Miyazoe, Masahiro Nakamura
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Patent number: 8871107Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
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Patent number: 8865502Abstract: The present disclosure provides a method of forming a back side surface field of a solar cell without utilizing screen printing. The method includes first forming a p-type dopant layer directly on the back side surface of the semiconductor substrate that includes a p/n junction utilizing an electrodeposition method. The p/n junction is defined as the interface that is formed between an n-type semiconductor portion of the substrate and an underlying p-type semiconductor portion of the substrate. The plated structure is then annealed to from a P++ back side surface field layer directly on the back side surface of the semiconductor substrate. Optionally, a metallic film can be electrodeposited on an exposed surface of the P++ back side surface layer.Type: GrantFiled: June 10, 2010Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Kathryn C. Fisher, Nicholas C. M. Fuller, Satyavolu S. Papa Rao, Xiaoyan Shao, Jeffrey Hedrick
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Publication number: 20140273437Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicants: APPLIED MATERIALS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Mark Hoinkis, Chun Yan
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Patent number: 8765613Abstract: An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.Type: GrantFiled: October 26, 2011Date of Patent: July 1, 2014Assignees: International Business Machines Corporation, Zeon CorporationInventors: Josephine B. Chang, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Masahiro Nakamura
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Patent number: 8768337Abstract: The present disclosure relates generally to the field of base station power control in a mobile network. In various examples, base station power control in a mobile network may be implemented in the form of systems, methods and/or algorithms.Type: GrantFiled: October 26, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Yasunao Katayama, Arun S. Natarajan
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Patent number: 8768338Abstract: The present disclosure relates generally to the field of base station power control in a mobile network. In various examples, base station power control in a mobile network may be implemented in the form of systems, methods and/or algorithms.Type: GrantFiled: November 26, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Yasunao Katayama, Arun S. Natarajan
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Publication number: 20140124870Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.Type: ApplicationFiled: August 20, 2013Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Benjamin L. Fletcher, Nicholas C.M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe