Abstract: A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of electrical connections between the die and the substrate. In one embodiment, the through-holes in the interposer are filled flush with a resilient plastic conductive material and pressed against raised conductive structures on the die and substrate. The die, interposer, and substrate are maintained in electrical contact under compression. The compressing force can be removed to replace the die. In another embodiment, the interposer has embedded conductive elements which make contact with selected connections between the die and the substrate. Electrical connections between the conductive elements can be selectively effected to provide for "re-wiring" of connections to the die and substrate.

Abstract: A method for cleaning solder bumps on a substrate that may be employed in a flip-chip design, for example, is described. The method of cleaning includes placing the substrate having the solder bumps into a plasma reactor, introducing a source gas including nitrogen trifluoride gas into the plasma reactor, striking a plasma from the source gas in the plasma reactor, and forming a fluoride compound on the surface of the solder bump.

Abstract: An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a cavity in the package with a thermally conductive fluid, immersing a heat collecting portion of a heat pipe assembly into the fluid, and sealing the cavity. In order that the thermally conductive fluid does not chemically attack the die or its electrical connections, the die and connections can be completely covered with an encapsulating coating of an inorganic dielectric material, such as silicon dioxide, by any of a variety of techniques. The heat pipe provides highly efficient heat transfer from within the package to an external heat sink by means of an evaporation-condensation cooling cycle. The optional dielectric coating over the die permits selection of the thermally conductive fluid from a wider range of fluids by isolating the die and its electrical connections from direct contact with the fluid.

Abstract: A method for cleaning solder bumps on a substrate that may be employed in a flip-chip design, for example, is described. The method of cleaning includes placing the substrate having the solder bumps into a plasma reactor, introducing a source gas including nitrogen trifluoride gas into the plasma reactor, striking a plasma from the source gas in the plasma reactor, and forming a fluoride compound on the surface of the solder bump.

Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: An electronic system utilizing at least one semiconductor die having raised conductive bumps on its surface for connecting to other devices or systems is disposed on a face of a preformed planar structure (interposer) having through holes. Solder joints with conductive bumps on an underlying substrate are formed in the through holes. In one embodiment, the interposer is dissolvable. In another embodiment, the through holes are at least partially filled with a conductive material for electrically connecting to the die. In another embodiment, the through holes are angled so that the interposer acts as a pitch spreader or adapter. In another embodiment, ball bumps are disposed on a side of the interposer away from the die. In the electronic system, a semiconductor die may be disposed on a side of an optically transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer.

Abstract: A substrate holder assembly for immobilizing an integrated circuit (IC) wafer during polishing is described. The substrate holder includes a base plate sized to support the integrated circuit (IC) wafer, a circumferential restraint member arranged with respect to the base plate to engage the IC wafer's edges and a carrier assembly disposed above the base plate and below the IC wafer. The carrier assembly includes a film having a surface that is characterized by a substantially oblate spheroid or hyperboloid surface of rotation, wherein the surface of the film is capable of supporting the IC wafer in a manner causing the IC wafer to bow according to the surface of rotation.

Abstract: A process for lowering the dielectric constant of a layer on a semiconductor wafer is described. The presence of the fullerene in the composite layer changes its dielectric constant. The process forms, on the wafer, a composite layer comprising matrix-forming material and a fullerene. The fullerene may be removed from the composite layer to leave an open porous layer. Removing the fullerene may be accomplished, for example, by contacting the composite layer with a liquid which is a solvent for the fullerene but not for the insulation material or by oxidizing the fullerene. The processes and insulation layers described are particularly useful for integrated circuits.

Abstract: A modular multi-pin package for an integrated circuit die is formed of simple standardized parts and a readily redesigned, integrated circuit specific circuit substrate possessing a design pattern for providing electrical connection between die pads and output pins. The substrate includes a pattern of electrically conductive traces each terminating in a die pattern at an interior portion of the substrate and terminating in a pattern of pin connecting pads at a peripheral portion of the substrate. A pin holding frame is formed with a plurality of holes in which are inserted a selected number and pattern of package terminal pins, each having a shank protruding outwardly from the pin holder for connection to external circuits or components and each having an inner head pressed against one of the pin connecting pads of the substrate circuit traces.

Abstract: According to the present invention, there is provided a method for fabricating a field effect transistor having reduced hot electron effects. In one embodiment, the method comprises the steps of disposing a gate oxide layer on a semiconductor substrate; disposing a gate material on the gate oxide layer; masking a portion of the gate material; anisotropically etching a gate structure into the gate material such that a trench is formed in the semiconductor substrate; implanting a source structure in the semiconductor substrate, the source structure having a first doping region superjacent a second doping region, the second doping region being lightly doped relative to the first doping region.

Abstract: An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon reins a high resistance and a good insulator.

Abstract: A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.

Abstract: An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil.

Abstract: An electronic system utilizing at least one integrated circuit that has reduced drive requirements for the input and output pads of the integrated circuit die. The integrated circuit of the system has an intermediate structure added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance of the integrated circuit to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate of the integrated circuit to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount.

Abstract: An integrated circuit structure is described having a non-metallic electrically conductive plate preferably placed over an insulating layer formed over the uppermost layer of metal lines. The electrically conductive non-metallic plate is operative to terminate electric field lines emanating from at least some of the metal lines in the metal layers under the insulating layer beneath the non-metallic electrically conductive plate, particularly the uppermost metal lines, i.e., those spaced the farthest distance from the underlying semiconductor substrate. The conductive plate may be connected to either a ground line or a power line. In another embodiment, the non-metallic electrically conductive plate may be located between at least the uppermost layer of metal lines and one or more lower layers of metal lines, with insulating layers separating the non-metallic electrically conductive plate from such metal lines.

Abstract: A method of doping metal layers on integrated circuits to provide electromigration resistance and integrated circuits having metal alloy interconnects characterized by being resistant to electromigration are provided. The process consists of the steps of (1) depositing a film of a pure first conductive metal upon a semiconductor, (2) patterning and etching the deposited film, (3) subjecting the patterned conductive metal film to metallo-organic chemical vapor deposition in order to deposit upon the first deposited metal and not upon any semiconductive areas present in the patterned conductive metal film a doping amount of a second conductive metal different from the first metal, and (4) heating at a temperature sufficient to uniformly diffuse the second metal through the bulk of the patterned first conductive metal film.

Abstract: Remote electrical contacts for a semiconductor are produced by depositing a polysilicon layer over the entire surface of a semiconductor device and removing a portion of the polysilicon layer by chemi-mechanical polishing. The resulting structure is thereby provided with electrically isolated areas of polysilicon which constitute remote electrical contacts for the semiconductor device. The polysilicon layer or the isolated areas of polysilicon can be salicided to provide very low resistivity. Either the polysilicon layer or the salicide layer can be subjected to ion implantation to provide LDD regions.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.