Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: A technique for forming bump bonded semiconductor device assemblies is described wherein a die attach structure is disposed between a semiconductor die and a substrate. Bump bonds (conductive bump contacts) are formed between the die and the substrate, outside of the periphery of the die attach structure. The die attach structure has a "rippled" or egg-crate shaped shape or texture characterized by alternating positive and negative peaks. The die is attached (e.g., by an adhesive) to the positive peaks, and the substrate is attached to the negative peaks. The die attach has the effect of anchoring the die to the substrate and absorbing mechanical shocks which would otherwise be transmitted to the conductive bump contacts. This serves to improve the shock resistance of the chip/substrate assembly. The die attach structure can be made to match the coefficient of expansion of the bump bonds as well as that of the die.

Abstract: Poor sidewall coverage of vias in substrates for multi-chip modules is alleviated by forming pillars associated with conductors on an underlying metal wiring layer. In one embodiment, the pillars are disposed underneath the conductors, causing portions of the conductors to be pushed up through an overlying insulating layer towards a metal layer overlying the insulating layer. The pillars can be electrically conductive or insulating, and can be thermally conductive. In another embodiment, the pillars are disposed atop the conductors, thereby extending at least partially through the insulating layer. These pillars are electrically conductive.

Abstract: A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: Improved thermal and/or electrostatic discharge characteristics are realized in cavity-type semiconductor device assemblies by filling the cavity with either a thermally conductive fluid and/or an arc suppressing gas, or combinations thereof. The interior of the cavity, including the die, leads extending into the cavity, and connections between the die and the leads may be coated to provide protection from corrosive and/or electrical characteristics of the cavity-filling fluid (liquid or gas). The fluid may be introduced through a hole in a lid sealing the cavity, and the cavity is filled sufficiently that the fluid is in contact with the die at various spatial orientations of the package. A thermally-conductive fluid substantially filling the cavity provides improved thermal conduction from the die to the package body without the mechanical stress problems (e.g., thermally induced cracking) ordinarily associated with bonding solid materials to the die.

Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical polishing apparatus is disclosed. With two polishing pads, prior to assembly, a seal of material impervious to the chemical action of a polishing slurry is disposed about the perimeter of the interface between the pads. Preferably, the seal is a bead of silicon-based "gasket" material, such as General Electric silicon caulk (RTV) or Dow Corning silicon adhesive, and is disposed in a ring at a radius r' about one inch inward from the perimeter (circumference) of the pads. When the pads are assembled together, the bead squashes and (1) forms a seal, and (2) causes the periphery of the upper pad to curve upward--thereby creating a bowl-like reservoir for increasing the residence time of slurry on the face of the pad prior to overflowing the pad.

Abstract: A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material.

Abstract: A method of cleaning semiconductor substrates after polishing, particularly chem-mech polishing a semiconductor substrate to planarize a layer, to remove excess material from atop a layer, and to strip back a defective layer is disclosed. Aluminum oxide particles having a small, well controlled size, and substantially in the alpha phase provide beneficial results when polishing. A phosphoric acid cleaning solution is used. The aluminum oxide particles are soluble in the phosphoric acid solution, which does not significantly attack silicon dioxide. The phosphoric acid solution can include a small concentration of hydrofluoric acid to aid in removing silicon dioxide detritus from the surface of the wafer.

Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A continuous stream of such radiation is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The distortable-surface device is a surface acoustic wave device, a magnetostrictive device, or the like. The beam-blocking device is a beam stop, such as a knife edge, an aperture, or the like. The distortable-surface device can be selectively caused to reflect an incident beam of radiation past or into the beam-blocking device. In this manner, a continuous stream of radiation, such as from a pellet of Cobalt-60, can be quickly and precisely gated on and off to impact and to not-impact the semiconductor wafer, respectively. By moving either of the reflected beam or the semiconductor wafer, line features can be created in the sensitized layer on the semiconductor wafer.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of reflow solder joints between conductive bumps on the die and corresponding conductive bumps of the substrate. In one embodiment, conductive elements embedded in the preformed planar structures extend at least partially into the through holes, forming electrical connections with the corresponding solder joints. The conductive elements can be used to electrically connect one solder joint to another within the interposer, and/or may extend beyond an edge of the interposer to provide for electrical probing of or connection to the solder joints. In one embodiment, the conductive elements are extended outside of the preformed planar structure to form "pins" or leads of the flip-chip structure.

Abstract: Techniques for identifying and determining the orientation, magnitude, and direction of slip plane dislocations transecting semiconductor dies are described, whereby a four point alignment pattern is examined for "squareness" and size integrity. Lack of squareness or significant change in apparent size of various aspects of the alignment pattern indicate slip-plane dislocations. The magnitude, orientation and direction of the dislocations are determined geometrically from measurement of the alignment pattern. Various other aspects of the invention are directed to optimal alignment of a photolithographic mask to a die which has experienced a slip-plane dislocation, and to discrimination between slip-plane dislocation and die-site rotation.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion 58 region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.

Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.

Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

Abstract: Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.