Patents by Inventor Nicholas F. Pasch

Nicholas F. Pasch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5247153
    Abstract: The surface of an optical element, such as the taking lens in semiconductor photolithographic apparatus, is deformed, in situ, by applying heat to the surface. A recipe for applying the heat to a selected area of the lens surface is developed by either measuring the image projected by the lens and comparing the measured image to the specified (mask) image, or by measuring the contour of the surface of the lens and comparing the measured contour to the lens' specified contour. The heat is applied by a laser, the output of which is focussed and scanned onto the surface of the lens. Method and apparatus are disclosed.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: September 21, 1993
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5225358
    Abstract: Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.
    Type: Grant
    Filed: August 23, 1991
    Date of Patent: July 6, 1993
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5217566
    Abstract: A glass passivation layer is deposited, densified and polished. Thereby an underlying wafer containing substantially defined devices is exposed to a temperature cycle that is sufficient for densification of the glass, and no more. Reflow and its attendant additional temperature cycle are thereby avoided, allowing for smaller, faster devices to be fabricated. Increased control over the ultimate thickness of the glass layer is also provided.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: June 8, 1993
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Roger Patrick
  • Patent number: 5168346
    Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: December 1, 1992
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Vahak K. Sahakian, Conrad J. Dell'Oca
  • Patent number: 5111279
    Abstract: A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces.
    Type: Grant
    Filed: August 30, 1990
    Date of Patent: May 5, 1992
    Assignee: LSI Logic Corp.
    Inventors: Nicholas F. Pasch, Vahak K. Sahakian, Conrad J. Dell'Oca
  • Patent number: 5082792
    Abstract: A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the resistance of the diffused region is changed in a known and predictable fashion and may be measured electrically, giving indirect but accurate evidence of contact size in a completely nondestructive fashion. The measurements may be made on completed devices. Method and structure are disclosed.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: January 21, 1992
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Philippe Schoenborn
  • Patent number: 5055871
    Abstract: Enhanced uniformity of illumination is achieved in photolithography by interposing photochromic glass in the light path between the illuminator light source and a semiconductor wafer. In one embodiment of the invention, the photochromic glass is disposed immediately adjacent and before (upstream of) the mask. In another embodiment of the invention, the photochromic glass is disposed upstream of the mask, and an intermediate lens is disposed between the photochromic glass and the mask. In a still further embodiment of the invention, the photochromic glass is disposed in a reflector behind the illuminator light source. In other embodiments of the invention. The photochromic glass is disposed downstream of the mask. In yet another embodiment of the invention, the photochromic glass is exposed by two or more copies of a mask on a reticle to effect averaging. The photochromic glass is then used as a virtual mask to expose the wafer. Each of the described embodiments has its own advantages.
    Type: Grant
    Filed: October 5, 1989
    Date of Patent: October 8, 1991
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 4708770
    Abstract: A process for forming vias in semiconductor structures includes the step of forming a pillar on an underlying dielectric layer prior to deposition of the metallization layer. The pillar is located above the diffusion region preferably and serves to provide substantially equal distances or heights for etching vias from the top planarized surface to the metallization layer deposited over the field oxide region and over the diffusion region.
    Type: Grant
    Filed: June 19, 1986
    Date of Patent: November 24, 1987
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 4652134
    Abstract: A system for aligning a semiconductor wafer with a mask bearing a pattern to be formed on the wafer, in which both the wafer and the mask bear an alignment mark, and in which light used for alignment is filtered to transmit only in a selected bandwidth, uses a reflector system to gather light reflected from edges of the alignment mark on the wafer. In order to minimize the effect of erroneous alignment signals from standing waves generated when the alignment signal is reflected from a wafer coated with a layer of photoresist, a second filter is placed in the path of light after it has reflected from the target. This second filter transmits a range of the reflected light which does not produce standing waves.
    Type: Grant
    Filed: August 28, 1984
    Date of Patent: March 24, 1987
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, James L. Hubbard