Abstract: Fine, sub-micron line features and patterns are created in a radiation sensitive resist layer on a semiconductor wafer by a beam of short wavelength gamma rays. The resist layer includes photoresist which is substantially chemically inactive in response to the gamma rays. The photoresist is either doped or covered with a material that absorbs gamma rays and in response emits secondary radiation of a different wavelength, preferably photons, that is actinic with respect to the photoresist. The resist layer enables using radiation sources having better resolving ability than conventional photolithographic sources to perform near-field and direct-write lithography.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into, the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.

Abstract: A laser is used to cut or "zap" unwanted sections of an aluminum interconnect metallization pattern on a microelectronic circuit substrate. Vaporized aluminum forms a cloud above the substrate that is reacted with a gas to form a substance which can be prevented from solidifying and forming a conductive residue on the substrate that could create a short circuit in the metallization pattern. The gas can be pressurized oxygen, in which case the reactant substance is electrically insulative aluminum oxide that forms a desirable sealing coating over the cut area. The aluminum oxide has a lower density than aluminum, and expands in the cut area to form a hermetic seal with the facing edges of the metallization pattern. Alternatively, the gas can be chlorine or other material which forms a residue that can be easily removed using a solvent such as water.

Abstract: Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.

Abstract: The present invention relates to a method of and system for reducing the drive requirements for the input and output pads of an integrated circuit die. An intermediate structure is added between the output connection pad and substrate to reduce the amount of electron charge required to charge the output pad capacitance to a substantially negligible amount. In addition, an intermediate structure may be added between an input connection pad and substrate to reduce the amount of electron charge required to charge the input pad capacitance to a substantially negligible amount. The present invention connects a transistor amplifier driver to the intermediate structure between the output pad and substrate to charge the capacitance that exists between the intermediate structure and substrate so that the voltage potential of the intermediate structure is substantially the same value as the output pad voltage value.

Abstract: A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

Abstract: A process of interconnecting a semiconductor device to a substrate wherein solder balls on the semiconductor device are fused with one side of an embedded noble metal foil within a through hole in an interposer structure. Solder balls on the substrate are fused with the metal foil within the structure window on the other side of the metal foil.

Abstract: A ring-shaped, substantially planar structure is described for interposing between a chip and a substrate. The ring-shaped structure, being more flexible than a similar solid structure, conforms more readily to any irregularities in the surface of the substrate. Through holes in the planar structure facilitate controlled formation of reflow solder connections between the chip and the substrate. In one embodiment, the ring shape of the planar structure has a gap to facilitate better conformance to irregularities in the surface of the substrate and to minimize "levering" of the chip. Other embodiments provide for "kerfing" of the ring-shaped planar structure to permit even greater flexibility of the structure and less levering of the chip. Angled through holes permit adaptation of mismatched solder bump patterns on the chip and substrate.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.

Abstract: A technique is describe for effecting very-high resolution semiconductor lithography using direct-write afocal electron-beam exposure of a sensitized wafer. A positioning mechanism and needle-like probe similar to those used in scanning-tunneling microscopy are used in conjunction with a controllable electron field emission source to produce a near-field electron beam capable of exposing an electron-beam sensitive resist on a wafer surface. Conventional e-beam resists are used. The technique can be used in conjunction with scanning-tunneling-like operation of the apparatus to record the appearance and nature of the wafer surface, thereby providing information about the location of underlying features. This location information can be used to assist in aligning the exposure patterns to existing structures in the semiconductor wafer.

Abstract: Positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate. The inventive technique is useful for joining die-to-die, die-to-substrate, or package-to-substrate.

Abstract: Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A process for interconnecting conductive substrates using an interposer having conductive plastic filled vias. The process comprises the steps of forcing conductive plastic material through an end of the through holes in the interposer so that raised globs of the conductive plastic extend from an opposite end of the through holes. Then conductive pads of a first substrate are aligned and pressed against the raised globs such that the conductive plastic protrudes as bumps from the forcing ends of the through holes. Finally, conductive pads of a second substrate are aligned and pressed against the bumps.

Abstract: An apparatus and method for mounting and connecting a plurality of integrated circuit chip dice to a printed circuit substrate by means of a small circuit board (such as a Mini-Board) that may be adapted to attach and connect into a plurality of different types of printed circuit board systems. A pattern of conductors that monotonically increases in pitch and width from a central point on a planar structure to the perimeter edge of the structure allows matching of any type of printed circuit board connections. A standard Mini-Board may be fabricated and tested before attaching to an electronic system printed circuit board. Repair and rework is easily facilitated with a minimum amount of damage to a printed circuit board by utilizing the present invention. A plurality of active and passive electronic components may also be attached and connected to the planar structure of the present invention. A hybrid mini-system may be fabricated and tested before connecting it into a system printed circuit board.

Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads.

Abstract: Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.