Patents by Inventor NICHOLAS POLOMOFF
NICHOLAS POLOMOFF has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220308297Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.Type: ApplicationFiled: March 23, 2021Publication date: September 29, 2022Inventors: Nicholas A. Polomoff, John J. Ellis-Monaghan, Frank G. Kuechenmeister, Jae Kyu Cho, Michal Rakowski
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Publication number: 20220291464Abstract: Structures including an edge coupler and a crackstop, as well as methods of forming a structure including an edge coupler and a crackstop. A waveguide core and a crackstop are located over a top surface of a dielectric layer. A communication passageway is either optically coupled or electrically coupled to the waveguide core. The communication passageway, which may include an electric conductor or a buried waveguide core, extends laterally beneath the crackstop.Type: ApplicationFiled: March 9, 2021Publication date: September 15, 2022Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Frank Kuechenmeister, John J. Ellis-Monaghan, Michal Rakowski
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Publication number: 20220057445Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.Type: ApplicationFiled: November 5, 2021Publication date: February 24, 2022Inventors: Nicholas A. Polomoff, Dewei Xu, Eric D. Hunt-Schroeder
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Patent number: 11215661Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.Type: GrantFiled: May 12, 2020Date of Patent: January 4, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Nicholas A. Polomoff, Dewei Xu, Eric D. Hunt-Schroeder
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Publication number: 20210375788Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Publication number: 20210356514Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit incudes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Inventors: Nicholas A. Polomoff, Dewei Xu, Eric D. Hunt-Schroeder
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Patent number: 11145606Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: GrantFiled: March 26, 2020Date of Patent: October 12, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Publication number: 20210305172Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Patent number: 11105846Abstract: Embodiments of the disclosure provide a system for detecting and monitoring a crack in an integrated circuit (IC), including: at least one electrically conductive perimeter line (PLINE) extending about, and electrically isolated from, a protective structure formed in an inactive region of the IC, wherein an active region of the IC is enclosed within the protective structure; a circuit for sensing a change in an electrical characteristic of the at least one PLINE, the change in the electrical characteristic indicating a presence of a crack in the inactive region of the IC; and a connecting structure for electrically coupling each PLINE to the sensing circuit.Type: GrantFiled: April 2, 2020Date of Patent: August 31, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Nicholas A. Polomoff, Dirk Breuer, Eric D. Hunt-Schroeder, Bernhard J Wunder, Dewei Xu
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Patent number: 11037873Abstract: A barrier or “crackstop” that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.Type: GrantFiled: June 3, 2019Date of Patent: June 15, 2021Assignee: MARVELL GOVERNMENT SOLUTIONS, LLC.Inventors: Nicholas A. Polomoff, Igor Arsovski, Mark W. Kuemerle
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Publication number: 20200381355Abstract: A barrier or “crackstop” that is configured to conduct electrical signals. These configurations may form a wall around integrated, active circuitry of a semiconductor die. This wall may include a conductor that follows a three-dimensional pathway from one side to the other side of the wall. This pathway may have sections that overlap, or double-back, so that portions of the conductor overlap along their individual length. These sections prevent crack propagation internal to the wall.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Applicant: Avera Semiconductor LLCInventors: Nicholas A. Polomoff, Igor Arsovski, Mark W. Kuemerle
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Patent number: 10770407Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: GrantFiled: January 4, 2019Date of Patent: September 8, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, Jr., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Patent number: 10770412Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element.Type: GrantFiled: August 23, 2018Date of Patent: September 8, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Nicholas A. Polomoff, Andreas D. Stricker, Anupam I Arora
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Patent number: 10714411Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: GrantFiled: March 15, 2018Date of Patent: July 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
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Publication number: 20200219826Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, JR., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Publication number: 20200066656Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element.Type: ApplicationFiled: August 23, 2018Publication date: February 27, 2020Inventors: Nicholas A. Polomoff, Andreas D. Stricker, Anupam I. Arora
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Patent number: 10546822Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.Type: GrantFiled: August 30, 2017Date of Patent: January 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Nicholas A. Polomoff, Vincent J. McGahay
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Patent number: 10438902Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.Type: GrantFiled: September 7, 2017Date of Patent: October 8, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Vincent J. McGahay, Nicholas A. Polomoff, Shaoning Yao, Anupam Arora
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Publication number: 20190287879Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
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Publication number: 20190074253Abstract: The present disclosure relates to semiconductor structures and, more particularly, to arc resistant crackstop structures and methods of manufacture. The structure includes: a crackstop structure comprising dual rails surrounding an active area of an integrated circuit; and a through-BOx electrical contact electrically connecting each of the dual rails to an underlying substrate.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Inventors: Vincent J. MCGAHAY, Nicholas A. POLOMOFF, Shaoning YAO, Anupam ARORA