Patents by Inventor NICHOLAS POLOMOFF
NICHOLAS POLOMOFF has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190067210Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Nicholas A. Polomoff, Vincent J. McGahay
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Patent number: 10153232Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.Type: GrantFiled: April 26, 2017Date of Patent: December 11, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
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Publication number: 20180315707Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.Type: ApplicationFiled: April 26, 2017Publication date: November 1, 2018Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
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Patent number: 10109600Abstract: The present disclosure relates to semiconductor structures and, more particularly, to continuous crackstop structures and methods of manufacture. The structure includes a continuous crackstop having a wall which switches back (switchbacks) on itself multiple times to form an enclosure about an active area of a chip.Type: GrantFiled: September 12, 2017Date of Patent: October 23, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Vincent J. McGahay, Nicholas A. Polomoff
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Patent number: 10090258Abstract: One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.Type: GrantFiled: September 25, 2017Date of Patent: October 2, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Kevin Boyd, Robert Fox, Jeannine Trewhella, Roderick Alan Augur, Nicholas A. Polomoff
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Patent number: 10068859Abstract: A structure for arresting the propagation of cracks during the dicing of a semiconductor wafer into individual chips includes a monolithic metallic plate that traverses multiple dielectric layers peripheral to an active region of a chip. One or more metallic plates may be formed using lithography and electroplating techniques between the active device region and a peripheral kerf region, where each metallic plate includes a concave feature that faces the kerf region of the wafer.Type: GrantFiled: July 28, 2017Date of Patent: September 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Nicholas A. Polomoff, Mohamed Rabie, Victoria L. Calero Diaz Del Castillo, Danielle Degraw, Michael Hecker
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Publication number: 20180082965Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.Type: ApplicationFiled: November 15, 2017Publication date: March 22, 2018Applicant: SUSS MicroTec Photonic Systems Inc.Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
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Publication number: 20180076160Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.Type: ApplicationFiled: November 15, 2017Publication date: March 15, 2018Applicant: SUSS MicroTec Photonic Systems Inc.Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
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Patent number: 9824925Abstract: Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.Type: GrantFiled: June 11, 2015Date of Patent: November 21, 2017Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Kevin S. Petrarca, Nicholas A. Polomoff, Katsuyuki Sakuma
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Patent number: 9754823Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: GrantFiled: May 28, 2014Date of Patent: September 5, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SÜSS MICROTEC PHOTONIC SYSTEMS INC.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Patent number: 9748135Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: GrantFiled: August 18, 2015Date of Patent: August 29, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SUSS MICROTEC PHOTONIC SYSTEMS INC.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20170117241Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.Type: ApplicationFiled: October 22, 2015Publication date: April 27, 2017Applicant: SUSS MicroTec Photonic Systems Inc.Inventors: Brian M. Erwin, Brittany L. Hedrick, Nicholas A. Polomoff, TaeHo Kim, Matthew E. Souter
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Publication number: 20160365281Abstract: Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Mukta G. Farooq, Kevin S. Petrarca, Nicholas A. Polomoff, Katsuyuki Sakuma
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Publication number: 20160204028Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20160184926Abstract: An ablation system includes an ablation tool configured to generate an energy beam to ablate an energy-sensitive material formed on at least one embedded feature of a workpiece. The ablation tool selects an initial fluence and an initial pulse rate of the energy beam to ablate a first portion of the energy-sensitive layer. The ablation tool further reduces at least one of the initial fluence and the initial pulse rate of the energy beam to ablate a second remaining portion of the energy-sensitive layer such that the embedded feature is exposed without being damaged or deformed.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Courtney T. Sheets, Matthew E. Souter, Brian M. Erwin, Bouwe W. Leenstra, Nicholas A. Polomoff, Christopher L. Tessler
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Patent number: 9343420Abstract: Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.Type: GrantFiled: February 14, 2014Date of Patent: May 17, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Brian M. Erwin, Eric D. Perfecto, Nicholas A. Polomoff, Jae-Woong Nah
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Publication number: 20160074968Abstract: A laser etching system includes a laser source configured to generate a plurality of laser pulses during an etching pass. A workpiece is aligned with respect to the laser source. The workpiece includes an etching material that is etched in response to receiving the plurality of laser pulses. A mask reticle is interposed between the laser source and the workpiece. The mask reticle includes at least one mask pattern configured to regulate the fluence or a number of laser pulses realized by the workpiece such that a plurality of features having different depths with respect to one another are etched in the etching material.Type: ApplicationFiled: September 11, 2014Publication date: March 17, 2016Inventors: Matthew E. Souter, Brian M. Erwin, Nicholas A. Polomoff, Christopher L. Tessler
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Publication number: 20150357235Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20150348910Abstract: A structure including a stack of conformal layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers including a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another with the first layer being in direct contact with the dielectric layer, and a conductive feature located directly on top of the fourth layer within the opening.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, John J. Garant, Ekta Misra, Nicholas A. Polomoff, Jennifer D. Schuler
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Publication number: 20150348831Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicants: International Business Machines Corporation, SUSS MicroTec Photonic Systems Inc.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler