Abstract: A method including forming a stack of layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers comprising a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another, removing a first portion of the fourth layer outside the opening to expose a portion of the third layer, a second portion of the fourth layer remains within the opening, filling the opening with a metal by applying an electrical potential to the second layer during an electroplating technique in which the metal plates out on the fourth layer but does not plate out on the third layer, and removing portions of the first layer, the second layer, and the third layer to expose an upper surface of the dielectric layer between the opening and an adjacent opening.

Abstract: Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.