Patents by Inventor Nicolas Loubet

Nicolas Loubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200051872
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 13, 2020
    Inventors: Jing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
  • Publication number: 20200052107
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Fee Li Lie, Mona Ebrish, Ekmini A. De Silva, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Nicolas Loubet
  • Publication number: 20200044057
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, NICOLAS LOUBET, PIETRO MONTANINI
  • Publication number: 20200044053
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20200044058
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Patent number: 10553723
    Abstract: A method is provided of fabricating a microelectronic device including a semiconductor structure provided with semiconductor bars positioned above one another, the method including the following steps: creating, on a substrate, a stacked structure including an alternation of first bars containing a first material and having a first critical dimension and second bars containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions of the second bars before forming a source and drain block on the portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 4, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Remi Coquand, Nicolas Loubet, Shay Reboh, Robin Chao
  • Patent number: 10553705
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Patent number: 10546945
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Patent number: 10546942
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20200027791
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Publication number: 20200020808
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Nicolas LOUBET, Pierre MORIN
  • Publication number: 20190393076
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Applicant: International Business Machines Corporation
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Publication number: 20190393304
    Abstract: Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Michael A. Guillorn, Nicolas Loubet
  • Patent number: 10515965
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 24, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Nicolas Loubet
  • Publication number: 20190386113
    Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: International Business Machines Corporation
    Inventors: Nicolas Loubet, Julien Frougier, Wenyu Xu, Zhenxing Bi
  • Publication number: 20190378915
    Abstract: A nanosheet transistor includes a nanosheet stack having a plurality of nanosheet layers and a plurality of gate material layers stacked upon a substrate. The nanosheet stack further includes a first fin and a second fin, and at least one gate formed on the nanosheet stack. The transistor further includes at least one inner spacer disposed on at least one sidewall of the gate material layers and the at least one gate. The at least one inner spacer is formed of an oxide layer in which a thicker layer of the oxide layer is deposited on the sidewalls of the at least one gate and the gate material layers than a thickness of the oxide layer deposited on sidewalls the nanosheet layers. The transistor further includes at least one outer spacer formed on the at least one inner spacer. The at least one outer spacer is formed of a spacer dielectric material.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Kangguo Cheng, NICOLAS LOUBET
  • Patent number: 10505043
    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10497808
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 3, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Nicolas Loubet
  • Patent number: 10483393
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 10453736
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie