Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: The present disclosure provides an information processing method, an apparatus, an electronic device, and a storage medium. By establishing a session group including a first identity user and a second identity user in response to the first identity user satisfying a preset first condition, pushing a first session message for the first identity user within the session group according to a preset process node, and displaying a first information editing interface for the first identity user, in response to a first preset operation of the first identity user for the first session message, the present disclosure can achieve automatic group creation, automatic reminder through group session, and entry into a relevant information editing interface through group session, thereby achieving efficient distribution and processing of information.

Abstract: The present invention discloses a recombinant RBD trimer protein capable of simultaneously generating cross neutralization activity for various severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) epidemic strains. The RBD trimer protein is taken as an antigen and supplemented with an adjuvant to immunize an organism, so that a high-titer neutralizing antibody aiming at various SARS-CoV-2 epidemic strains can be generated at the same time, and the antibody has a certain broad-spectrum property and can be used for treating and/or preventing SARS-CoV-2 infection and/or coronavirus disease 2019.

Abstract: Self-aligned gate isolation/cutting techniques for multigate devices are disclosed herein. An exemplary multigate device includes a first gate having a gate stack that surrounds a semiconductor layer. The first gate is disposed between a first gate isolation wall and a second gate isolation wall. The gate stack has a gate dielectric and a gate electrode, the gate stack has a first sidewall and a second sidewall, and the first sidewall is formed by the gate dielectric and the gate electrode. A gate endcap is disposed on the first sidewall. A gate helmet is disposed over the gate stack, and a portion of the gate dielectric is disposed between the gate electrode and the gate helmet. A gate contact is disposed on the first gate. The gate contact extends over the first gate isolation wall and connects the first gate to a second gate.

Abstract: A method of improving grinding, grading and capacity of ores by reducing a fineness content ratio ?0 in settled ores includes providing a two-stage ore grinding and grading system including a first fully closed circuit including a grinder and a hydrocyclone, or a two-stage ore grinding and grading system including a first-stage open circuit, and controlling parameters for ore grinding and grading as follows: controlling a dc an value of a point B on a separation cone of a second-stage ?500 mm hydrocyclone; controlling a fineness content ratio ?0 in settled ores; controlling a second-stage ore grinding and grading load Q2; and acquiring a first-stage grinding, grading and capacity Q of ores.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to form a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Abstract: Systems and methods are described for suggesting personal graphical elements for inclusion in a conversation. At least one message in a conversation is analyzed to determine an emotion or sentiment and the conversation participants are identified. Personal graphical elements, labeled with metadata and associated emotions, are selected from a database.

Abstract: An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.

Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Abstract: A water jet strengthening and polishing integrated system for blades of a blisk includes a vibration polishing unit and a water jet strengthening unit. The vibration polishing unit includes a vibration polishing bath, the vibration polishing bath is internally provided with a clamp for clamping the blisk, and vibration motors for driving the vibration polishing bath to vibrate are installed on the vibration polishing bath. Top ends of support springs are fixedly connected with the vibration polishing bath, and bottom ends of the support springs are fixedly connected with a workbench. The water jet strengthening unit includes a water jet strengthening device for carrying out water jet strengthening on the blades of the blisk and a driving mechanism for clamping the water jet strengthening device and capable of driving the water jet strengthening device to move in any direction in space.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a channel structure over a substrate and forming a protective spacer over sidewalls of the channel structure. The method also includes forming an insulating wall adjacent to an end of the channel structure. The method further includes removing the protective spacer to expose the channel structure. In addition, the method includes forming a metal gate stack surrounding an intermediate portion of the channel structure.

Abstract: Thiazole-lactam-spiroheterocyclic compounds and applications thereof in the preparation of drugs for treating related diseases. Specifically disclosed are a compound as represented by formula (I) and pharmaceutically acceptable salts thereof.