Abstract: The present application relates to an aqueous positive electrode sheet, which may include a current collector and a positive electrode active substance layer provided on at least one surface of the current collector, the positive electrode active substance layer may include an aqueous binder, where the porosity of a surface area of the positive electrode active substance layer may be greater than the porosity of an inner area of the positive electrode active substance layer, and the average particle size of the positive electrode active material in the surface area may be greater than the average particle size of the positive electrode active material in the inner area. The present application further relates to a secondary battery including the aqueous positive electrode sheet, a battery pack including the secondary battery, and a power consumption apparatus including the battery pack.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

Abstract: A switching charger for accurately sensing a small current is provided. First terminals of first transistors and a second transistor are coupled to a system voltage. Second terminals of the first transistors and a first input terminal of an operational amplifier are connected to a battery. A first terminal of a third transistor is connected to a second terminal of the second transistor and a second input terminal of the operational amplifier. A control terminal of the third transistor is connected to an output terminal of the operational amplifier. A first terminal of a fourth transistor is connected to a second terminal of the third transistor. First terminals of fifth transistors are coupled to an input voltage. Control terminals of the first transistors and the fifth transistors are connected to a control circuit. First terminals of sixth transistors are respectively connected to second terminals of the fifth transistors.

Abstract: The present invention provides two forms of information interaction mechanisms and network transmission methods in a multimedia system. One is implementing bidirectional quick information interaction by using an interaction message body, so that the defect that there is no efficient and flexible bidirectional information interaction mechanism in existing media transmission systems can be overcome, and the mechanism is applicable to all media transmission systems. The other one is simplifying the size of protocol format header data for a simplest data packet forced by a protocol transmission format, so that the protocol format is quickly adapted to quick information interaction. The simplifying the size of protocol format header data can overcome the defect that there is no efficient bidirectional quick information interaction mechanism in the existing media transmission systems. In addition, an optimized transmission mechanism for a still image in a video stream is provided.

Abstract: A method for soldering a solar cell, includes: placing a plurality of back contact cells on a soldering platform, where back surfaces of the back contact cells face away from the soldering platform, and electrodes corresponding to two adjacent back contact cells have opposite polarities in a connection direction of a plurality of to-be-connected ribbons; placing the plurality of to-be-connected ribbons on the electrodes of the plurality of back contact cells by using a first clamping portion, a second clamping portion, and a plurality of third clamping portions, where the first clamping portion, the second clamping portion, and the plurality of third clamping portions respectively correspond to head ends, tail ends, and middle portions of the plurality of ribbons; and heating the plurality of ribbons by using a heater to connect the plurality of ribbons to the plurality of back contact cells.

Abstract: Provided is at least one of an improvement in the thermal stability of a CHA-type zeolite, which is achieved by a method different from that of the related art for improving thermal stability; a method for producing a CHA-type zeolite that improves thermal stability; and such a CHA-type zeolite. Provided is a CHA-type zeolite having a 1H-MAS-NMR spectrum and an IR spectrum in which, preferably, in the 1H-MAS-NMR spectrum, a ratio of an integrated intensity of a maximum peak having a peak top at a chemical shift of 3.0 to 3.5 ppm to an integrated intensity of a maximum peak having a peak top at a chemical shift of 4.0 to 4.5 ppm is greater than 0.12 and 0.5 or less, and, in the IR spectrum, a ratio of a maximum peak height of an absorption peak having a peak top at a wavenumber of 3630 cm?1 or greater and 3650 cm?1 or less to a maximum peak height of an absorption peak having a peak top at a wavenumber of 3590 cm?1 or greater and 3610 cm?1 or less is 0.40 or greater and 1.0 or less.

Abstract: An electronic device includes a substrate, a plurality of first retaining walls, a second retaining wall, and a light emitting element. The first retaining walls are arranged on the substrate. The second retaining wall is arranged on the substrate and disposed within one of the first retaining walls. The light emitting element is arranged on the substrate and disposed between the second retaining wall and one of the first retaining walls adjacent to the second retaining wall. In a cross section, there are a first distance between the light emitting element and the one of the first retaining walls, and a second distance between the light emitting element and the second retaining wall, wherein the second distance is smaller than the first distance.

Abstract: A backlight module includes a substrate, a plurality of light emitting elements, a light guide device and a plurality of reflective elements. The light emitting elements are arranged on the substrate. The light guide device includes a plurality of light guide portions arranged to respectively correspond to the light emitting elements, wherein each of the light guide portions is provided with a first through hole, and the first through holes of the light guide portions respectively expose the light emitting elements. The reflective elements are respectively arranged on the light emitting elements, wherein, in a normal direction of the substrate, the reflective elements respectively overlap with the first through holes of the light guide portions.

Abstract: A sensor is provided. A first terminal of a first current source and a first terminal of a first transistor are connected to a cathode of the photodiode. A control terminal of a second transistor is connected to an output terminal of a first operational amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor through a first current mirror circuit. A second terminal of the second transistor is connected to a second current source, a second input terminal of a second operational amplifier and a first terminal of a third transistor. A first input terminal of the second operational amplifier is connected to the first terminal of the first transistor. A control terminal of the third transistor is connected to an output terminal of the second operational amplifier.

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Abstract: Related to is a bidirectional capacitance - inductance - inductance - capacitance (CLLC) circuit with a coupled inductor, which is associated with a circuit topology and operation control of a bidirectional CLLC resonant converter. A bidirectional CLLC resonant circuit with a coupled inductor includes a primary side bridge, a secondary side bridge, a primary side resonant capacitor, a secondary side resonant capacitor, a coupled resonant inductor, and a transformer. Compared with a structure of a conventional bidirectional CLLC resonant circuit, two separate resonant inductors located at a primary side and a secondary side in an original resonant cavity are replaced with one coupled resonant inductor in the circuit; the coupled resonant inductor has opposite dotted terminals with the transformer, and a primary side and a secondary side of the coupled resonant inductor are respectively in serial connection with a primary side and a secondary side of the transformer.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.

Abstract: The present disclosure pertains to compositions comprising anti-VEGF proteins.

Abstract: A method for adjusting the uniformity of a display is provided. The method includes the following steps. An angle sensor is disposed on a display. The display opposite to a measurement device is disposed on a rotation axis. The uniformity of a frame of the display at at least one use angle is measured by the measurement device, wherein the display is adjusted to a first use angle and is left still for a period of time, so that the uniformity of the display arranged at the first use angle has a first uniformity correction parameter; and a correspondence table relevant to the first use angle and the first uniformity correction parameter is stored to the display.

Abstract: Disclosed herein are methods and compositions for detecting Bordetella pertussis and Bordetella parapertussis by detecting the presence of the IS481 and IS1001 genomic insertion sequences, respectively.

Abstract: A collaborative data schema management system for federated learning (i.e., federated data manager (FDM)) is provided. Among other things, FDM enables the members of a federated learning alliance to (1) propose data schemas for use by the alliance, (2) identify and bind local datasets to proposed schemas, (3) create, based on the proposed schemas, training datasets for addressing various ML tasks, and (4) control, for each training dataset, which of the local datasets bound to that training dataset (and thus, which alliance members) will actually participate in the training of a particular ML model. FDM enables these features while ensuring that the contents of the members' local datasets remain hidden from each other, thereby preserving the privacy of that data.