Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapped around the semiconductor nanostructures, and the gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The gate dielectric layer extends along and beyond first opposite sidewalls of the dielectric stressor structure.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: A method for making a semiconductor device includes forming a first fin structure including a first plurality of semiconductor layers vertically spaced from one another and over a substrate; forming a second fin structure including a second plurality of semiconductor layers vertically spaced from one another and over the substrate, the first and the second fin structures extend along a first lateral direction; forming a first dielectric structure extending into the substrate and parallel with the first and second fin structures, the second fin structure being separated from the first fin structure along a second lateral direction perpendicular to the first lateral direction, by a first distance; and forming a first gate structure that extends along the second lateral direction and wraps around each of the first plurality of semiconductor layers and each of the second plurality of semiconductor layers.

Abstract: A cantilever for gas flow direction control configured to support an electrode housing bowl in an associated etch process chamber. The cantilever may have a cross-section that is circular, elliptical, or airfoil shaped. The shape of the cantilever induces the flow of gas and etch products within the chamber around the cantilever, reducing turbulence around the edge of a wafer.

Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess and a second S/D recess. The method includes forming a first bottom layer in the first S/D recess and a second bottom layer in the second S/D recess, and forming a first dielectric liner layer over the first bottom layer. The method includes forming a first top layer over the first dielectric liner layer, and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

Abstract: A semiconductor structure includes a p-type metal-oxide semiconductor (PMOS) region and an n-type metal-oxide semiconductor (NMOS) region, first source/drain (S/D) features in the PMOS region and second S/D features in the NMOS region, a first channel region connecting the first S/D features and a second channel region connecting the second S/D features, a first high-k metal gate stack (HKMG) over the first channel region and a second HKMG over the second channel region, first gate spacers on sidewalls of the first HKMG and second gate spacers on sidewalls of the second HKMG, a first etch-stop layer (ESL) on the first S/D features and the first gate spacers and a second ESL on the second S/D features and the second gate spacers, an oxide layer on the first ESL but not the second ESL, and an interlayer dielectric (ILD) layer on the oxide layer and the second ESL.

Abstract: Systems and methods for navigating a video via interaction with text overlaid on the video are described. In one example, a method includes generating for display a video, and generating for display at least one line of text overlaid over the video. Then, in response to receiving a directional user interface input for at least a portion of the at least one line of text, the method includes modifying a play position of the video based on a direction of the directional user interface input for the at least a portion of the at least one line of text.

Abstract: A stylus pen includes a pen barrel extending along a longitudinal axis, and the pen barrel includes a main body, a pen nib part disposed at one end of the main body, and a pen end part disposed at another end of the main body and that corresponds to the pen nib part; and an antenna disposed on the main body of the pen barrel, where at least one part of the antenna is located outside the pen barrel and is close to the pen nib part and/or the pen end part, and the antenna comprises a loop antenna or a planar inverted-F antenna close to the pen end part.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.

Abstract: Antibodies that binds Nectin Cell Adhesion Molecule 4 (nectin-4) and multi-specific protein complexes comprising such anti-nectin4 antibodies, at least one additional antibody moiety binding to another target, and/or at least one cytokine moiety. Also provided herein are pharmaceutical compositions comprising such and uses thereof.

Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.