Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.

Abstract: Systems and methods are described for enabling a lensless camera having an image sensor and a mask to be positioned behind a display screen of a device, which allows for the device to have an increased screen-to-body ratio. The image sensor captures an image based on the light that travels through the display screen and the mask. The display screen may include portions between pixel elements that allow light to pass through. The mask may include a pattern, such as an opaque material with portions that allow light to pass through from the portions of the display layer to the image sensor. The image captured by the image sensor may be indiscernible to humans. The system may utilize a trained machine learning model to reconstruct the image, using data about the pattern of the mask, so humans may visually recognize features in the image.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

Abstract: Systems and methods are provided herein for providing consistent picture quality during live or non-live streaming of hybrid content. For example, a camera may capture a first piece of hybrid content depicting a scene. The scene may include one or more real objects (e.g., a first person conducting an interview) and a piece of content (e.g., a stream of a second person being interviewed) being displayed on a screen (e.g., television screen). A system may receive the first piece of hybrid content and the source of the piece of content being displayed within the scene. The system may then insert the source of the piece of content into the first piece of content, replacing the depiction of the piece of content, to generate a second piece of hybrid content. The second piece of hybrid content may then be transmitted to one or more devices.

Abstract: A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.

Abstract: The present invention relates to the field of animal health. Particularly, the present invention relates to a recombinant classical swine fever virus E2 protein comprising at least one mutation at the epitope specifically recognized by the 6B8 monoclonal antibody. Further, the present invention provides an immunogenic composition comprising the recombinant E2 protein of the present invention and the use of the immunogenic composition for preventing and/or treating diseases associated with CSFV in an animal. Moreover, the present invention provides a method and a kit for differentiating animals infected with CSFV from animals vaccinated with the immunogenic composition of the present invention. Furthermore, the present invention provides a method of producing the E2 protein.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes depositing a spacer layer over an isolation region between adjacent fin structures, and the spacer layer is formed on sidewalls and tops of the fin structures. The method further includes forming a mask on the spacer layer between the fin structures, and the mask has a height substantially less than a height of the fin structures. The method further includes removing portions of the spacer layer and recessing the fin structures to form a spacer and to expose a portion of each fin structure, the spacer includes a first portion having a “U” shape disposed on the isolation region, and the portion of each fin structure has a top surface located at a level substantially below a top surface of the isolation region. The method further includes removing the mask.

Abstract: The present disclosure belongs to the technical field of plant genetic engineering. An objective of the present disclosure is to increase an anthocyanidin content of a rice seed. The present disclosure provides use of ZlMYB1 and ZlMYB2 genes from Zizania latifolia in increasing an anthocyanidin content of a rice seed, where the ZlMYB1 gene has the nucleotide sequence set forth in SEQ ID NO: 1; and the ZlMYB2 gene has the nucleotide sequence set forth in SEQ ID NO: 2. In the present disclosure, the ZlMYB1 and ZlMYB2 genes can be effectively overexpressed in rice. When a growth environment is consistent with that of a control plant, rice seeds from a rice plant overexpressing the ZlMYB1 and ZlMYB2 genes turn black and have a significantly increased anthocyanidin content compared with those from the control plant.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

Abstract: An electrode structure, a display panel, an electronic device are provided, the electrode structure includes a first electrode portion, a second electrode portion and a conductive connection portion, the first electrode portion includes a first connection bar having a first side and a second side and a plurality of first electrode strips, ends of adjacent first electrode strips away from the first connection bar are open; the second electrode portion includes a second connection bar at a position of the first side away from the second side and a plurality of second electrode strips, the second connection bar includes a third side and a fourth side; the second electrode strips are connected with the second connection bar, ends of adjacent second electrode strips away from the second connection bar are open; ends of the conductive connection portion are connected with the first connection bar and the second connection bar.

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

Abstract: Methods for video decoding and encoding, apparatuses and non-transitory storage media are provided. In one decoding method, the decoder obtains a first candidate position and a second candidate position. The decoder obtains a third candidate position based on the first and second candidate positions and obtains a virtual block based on the first, the second, and the third candidate positions. The decoder may obtain a plurality of CPMVs for the virtual block based on translational MVs at the first, second, and third candidate positions; and project, the plurality of CPMVs for the virtual block to a current block to obtain a translational MV based on a specific position within the current block or a second plurality of CPMVs for the current block.

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes first nanostructures formed over a substrate, and a first gate electrode layer formed on the first nanostructures. The semiconductor structure includes a second gate electrode layer adjacent to the first gate electrode layer, and a protective layer formed over the first gate electrode layer and the second gate electrode layer. The semiconductor structure includes a first dielectric structure between the first gate electrode layer and the second gate electrode layer, and the first dielectric structure penetrates through the protective layer.

Abstract: Disclosed herein are high affinity anti-Siglec 15 antibodies and methods of using such for therapeutic and/or diagnostic purposes. Also provided herein are methods for producing such anti-Siglec 15 antibodies.

Abstract: A semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source/drain feature disposed on the first insulator layer, a second source/drain feature disposed on the second insulator layer. A thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.

Abstract: A water jet strengthening and polishing integrated system for blades of a blisk includes a vibration polishing unit and a water jet strengthening unit. The vibration polishing unit includes a vibration polishing bath, the vibration polishing bath is internally provided with a clamp for clamping the blisk, and vibration motors for driving the vibration polishing bath to vibrate are installed on the vibration polishing bath. Top ends of support springs are fixedly connected with the vibration polishing bath, and bottom ends of the support springs are fixedly connected with a workbench. The water jet strengthening unit includes a water jet strengthening device for carrying out water jet strengthening on the blades of the blisk and a driving mechanism for clamping the water jet strengthening device and capable of driving the water jet strengthening device to move in any direction in space.