Patents by Inventor Ning Chen

Ning Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210325719
    Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).
    Type: Application
    Filed: July 19, 2018
    Publication date: October 21, 2021
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE Technology Group Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Publication number: 20210328293
    Abstract: The present disclosure relates to a secondary battery and a battery module. The secondary battery includes a case including a receiving space with an opening; a cap assembly connected to the case and close the opening; an electrode assembly disposed in the receiving space and including two end faces opposite to each other in a first direction perpendicular to an axial direction of the receiving space, and tabs extending from the end faces and two or more electrode units stacked in the axial direction; and a current collecting unit, including a first piece extending in the axial direction and a first current collecting piece connected to the first piece, the tab extends in the first direction and is connected to the first current collecting piece, and a portion of the tab connected to the first current collecting piece and the first current collecting piece are stacked in the axial direction.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: Contemporary Amperex Technology Co., Limited
    Inventors: Ning Chen, Haizu Jin, Dongyang Shi, Zhenhua Li, Fei Hu, Yuanbao Chen
  • Publication number: 20210328304
    Abstract: The disclosure provides a battery pack, which includes a plurality of batteries and a box, the plurality of batteries accommodated in the box; each battery including an explosion-proof valve; the box including a lower box for supporting the batteries and an upper box matching the lower box, wherein the upper box includes an upper plate and a lower plate, the upper plate covers the lower plate to form an accommodating space for accommodating a fire extinguishing agent; the explosion-proof valve of each battery faces the lower plate of the upper box, and the lower plate is set to be able to discharge the fire extinguishing agent from the accommodating space after being melted. When the battery occurs a thermal runaway, the fire extinguishing agent in the lower plate flows rapidly to the runaway area, thus inhibiting the thermal runaway of the battery.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Kaijie YOU, Peng WANG, Haizu JIN, Dongyang SHI, Zhenhua LI, Ning CHEN, Fei HU
  • Publication number: 20210327966
    Abstract: The present application relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base plate, a plurality of pixel structures on the base plate, and a color resist layer on a side of the plurality of pixel structures away from the base plate. The color resist layer includes a plurality of color resist blocks, each color resist block corresponding to one or more of the plurality of pixel structures. Light emitted from each of the plurality of pixel structures has the same color as the color resist block corresponding thereto.
    Type: Application
    Filed: April 4, 2019
    Publication date: October 21, 2021
    Inventors: Can WANG, Can ZHANG, Xiaochuan CHEN, Minghua XUAN, Han YUE, Ming YANG, Ning CONG
  • Publication number: 20210325792
    Abstract: An alignment structure is provided. The alignment structure includes a substrate, an alignment portion, and an extension portion. The alignment portion is disposed on the substrate. The extension portion is disposed on the substrate. The extension portion at least partially surrounds the alignment portion and is spaced apart from the alignment portion by a void. A side of the extension portion adjacent to the alignment portion and a side of the alignment portion adjacent to the extension portion are conformal to each other.
    Type: Application
    Filed: November 2, 2020
    Publication date: October 21, 2021
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yen-Yeh Chen, Shiang-Ning Yang, Chih-Ling Wu, Yu-Ya Peng
  • Patent number: 11153651
    Abstract: The present disclosure provides a methods, an apparatus and a device for obtaining play data, and a storage medium, including: receiving request information sent by a user, and transmitting the request information to a server, so that the server searches VOD data and EPG data simultaneously according to the request information, where the EPG data includes live broadcast data and live broadcast playback data; receiving the VOD data and the EPG data sent by the server; displaying the VOD data and the EPG data simultaneously, when the VOD data and the EPG data are determined to have been received. Therefore, the VOD data and the EPG data may be searched simultaneously, and the terminal device may simultaneously obtain the VOD data and the EPG data, allowing the user to obtain the VOD data and the EPG data simultaneously, so as to facilitate the user to watch the data in time.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 19, 2021
    Inventors: Zhike Zhang, Fei Wang, Jiaguang Lu, Zhouwei Zhai, Wenlin Dong, Hongwei Ma, Zhaoji Xu, Sheng Chen, Weiwen Gao, Ning Li
  • Publication number: 20210318245
    Abstract: An integrated spectro-microscopic system for multimodality imaging on a sample includes a reflected differential interference contrast (RDIC) microscope, a Raman spectroscope optically coupled with the RDIC microscope and a total internal reflection fluorescence/scattering (TIRF/TIRS) microscope optically coupled with the RDIC microscope such that the integrated spectro-microscopic system is capable of simultaneously acquiring both the RDIC images, the Raman spectra and TIRF/TIRS images on the same sample.
    Type: Application
    Filed: August 16, 2019
    Publication date: October 14, 2021
    Inventors: Ning FANG, Bin DONG, Kuangcai CHEN, Fei ZHAO
  • Publication number: 20210320383
    Abstract: The present application relates to a current collector and a secondary battery. The current collector is used to electrically connect a pole and tab of a secondary battery, and comprises: a first sheet; a second sheet that is disposed to intersect the first sheet, the second sheet being used to electrically connect to the pole; a current collection unit, the current collection unit and the second sheet being disposed at two opposite sides of the first sheet in a first thickness direction thereof, and the first thickness direction thereof intersecting with a second thickness direction of the second sheet; the current collection unit comprises a first current collection sheet, the first current collection sheet is used to electrically connect to the tab, and the first current collection sheet is provided with a first connection terminal that is connected to the first sheet.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Applicant: Contemporary Amperex Technology Co., Limited
    Inventors: Yuanbao CHEN, Dongyang SHI, Ning CHEN, Haizu JIN, Zhenhua LI, Fei HU
  • Publication number: 20210319109
    Abstract: The present disclosure is directed to reducing the secure boot time of software images and includes one or more processors and one or more computer-readable non-transitory storage media coupled to the one or more processors and comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including identifying a software image for a first secure boot, the software image stored in a persistent storage and comprising a kickstart software package and a system software package, fetching the software image, including the kickstart software package and the system software package, from the persistent storage to a memory, verifying one or more digital signatures associated with the software image, booting the kickstart software package of the software image from the memory, and staging the system software package in the persistent storage.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: Wenwei Weng, Nag Avadhanam, Xiaoguang Chen, Ning Zhao, Christopher A. Stone
  • Publication number: 20210315473
    Abstract: A method for analyzing an electrocardiography (ECG) signal is provided. The ECG signal is measured through a sensor. One or more specified waveforms in the ECG signal are detected. Multiple ECG features from each specified waveform are captured. The ECG features are input into multiple candidate models to obtain multiple candidate scores. Each candidate score is compared with a standard value to obtain an ideal score among the candidate scores. One of the candidate models corresponding to the ideal score is selected as a risk prediction model to predict disease risk through the risk prediction model.
    Type: Application
    Filed: May 13, 2020
    Publication date: October 14, 2021
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Yun-Hsuan Chan, Ke-Han Pan, Wei-Ju Li, Liang-Kung Chen, Li-Ning Peng
  • Publication number: 20210315760
    Abstract: A method for performing lower limb rehabilitation training comprises the steps of: (a) placing a training object's feet on a pedal in a limb rehabilitation training system, wherein the pedal comprises a pressure sensor and a location information sensor; (b) standing stably on the pedal to enable the pressure sensor on the pedal to record the body weight of the training object; and (c) sitting down on the saddle, thereby enabling: the pressure sensor on the pedal to monitor pressure variation between the training object and the pedal throughout the training of the training object, wherein the rehabilitation evaluating unit evaluates the physical status and rehabilitation status of the training object according to the physiological information and exercise information of the same collected by the sensing unit, and adjusts the exercise frequency and the exercise duration of the training object according to the physical status.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Ping ZHAO, Jiaoyun YANG, Ning AN, Lihong ZHU, Bing CHEN, Tianjun GUAN, Liang ZHANG, Ping ZHANG
  • Publication number: 20210320210
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO
  • Patent number: 11145752
    Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Ning Feng, Chih-Chang Hung, Bing-Hung Chen, Yih-Ann Lin
  • Publication number: 20210313514
    Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
  • Publication number: 20210313661
    Abstract: The present application relates to a secondary battery and a battery module. The secondary battery comprises: a casing, which is provided with an accommodating hole with an opening; a top cover assembly, which is in sealed connection with the casing to close the opening; an electrode assembly, which is arranged in the accommodating hole, and comprises two end faces opposite to a first direction perpendicular to an axial direction of the accommodating hole, and tabs extending from the end faces, the electrode assembly comprises two or more electrode units, wherein two or more electrode units are stacked in the axial direction, and in a second direction perpendicular to the axial direction and the first direction, the size of the tabs is smaller than that of the end faces; and a current collector, which comprises a body portion.
    Type: Application
    Filed: June 20, 2021
    Publication date: October 7, 2021
    Applicant: Comtemporary Amperex Technology Co., Limited
    Inventors: Yuanbao CHEN, Rui Yang, Haizu Jin, Dongyang Shi, Ning Chen, Quankun Li
  • Patent number: 11139540
    Abstract: The present disclosure relates to a battery module and a battery pack. The battery module comprises two or more secondary batteries arranged side by side in a first direction, each of which includes a case, an electrode assembly and a closing portion, wherein the case has a receiving hole comprising an opening and extending in a second direction, and the first direction intersects with the second direction, wherein the closing portion is sealingly connected with the case to close the opening, the electrode assembly is disposed in the receiving hole and includes two or more electrode units, the electrode unit includes a first electrode plate, a second electrode plate and a separator, and the two or more electrode units are stacked in the second direction.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 5, 2021
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Haizu Jin, Dongyang Shi, Zhenhua Li, Xingdi Chen, Ning Chen, Fei Hu
  • Patent number: 11139432
    Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Miao Liu, Bwo-Ning Chen, Kei-Wei Chen
  • Publication number: 20210305456
    Abstract: The present disclosure provides a semiconductor light-emitting device and a semiconductor light-emitting component. The semiconductor light-emitting device includes a substrate, a first semiconductor contact layer, a semiconductor light-emitting stack including an active layer, a first-conductivity-type contact structure, a second semiconductor contact layer, a second-conductivity-type contact structure and a first electrode pad. The first-conductivity-type contact structure is electrically connected to the first semiconductor contact layer. The second-conductivity-type contact structure is electrically connected to the second semiconductor contact layer. The first-conductivity-type contact structure has a first bottom surface and a first top surface, and the active layer has a second bottom surface and a second top surface.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Inventors: Jian-Zhi CHEN, Yen-Chun TSENG, Hui-Fang KAO, Yao-Ning CHAN, Yi-Tang LAI, Yun-Chung CHOU, Shih-Chang LEE, Chen OU
  • Patent number: 11133386
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu
  • Patent number: 11124780
    Abstract: The present disclosure relates to a genetically engineered strain with high production of uridine and its construction method and application. The strain was constructed as follows: heterologously expressing pyrimidine nucleoside operon sequence pyrBCAKDFE (SEQ ID NO:1) on the genome of E coli prompted by strong promoter Ptrc to reconstruct the pathway of uridine synthesis; overexpressing the autologous prsA gene coding PRPP synthase by integration of another copy of prsA gene promoted by strong promoter Ptrc on the genome; deficiency of uridine kinase, uridine phosphorylase, ribonucleoside hydrolase, homoserine dehydrogenase I and ornithine carbamoyltransferase. When the bacteria was used for producing uridine, 40-67 g/L uridine could be obtained in a 5 L fermentor after fermentation for 40-70 h using the technical scheme provided by the disclosure with the maximum productivity of 0.15-0.25 g uridine/g glucose and 1.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Tianjin University of Science and Technology
    Inventors: Xixian Xie, Ning Chen, Heyun Wu, Guoliang Li, Qiang Li, Xiaoguang Fan, Qingyang Xu, Chenglin Zhang, Yanjun Li, Qian Ma