Patents by Inventor Ning Chen

Ning Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250034167
    Abstract: The present disclosure provides compounds useful for the inhibition of KRAS G12D. The compounds have a general Formula (I): wherein the variables of Formula I are defined herein. This disclosure also provides pharmaceutical compositions comprising the compounds, uses of the compounds, and compositions for treatment of, for example, cancer.
    Type: Application
    Filed: August 10, 2022
    Publication date: January 30, 2025
    Applicant: AMGEN INC.
    Inventors: Michael M. YAMANO, Yunxiao LI, Primali Vasundera NAVARATNE, Jose M. MEDINA, Ning CHEN, Liping PETTUS, Rene RAHIMOFF, Xiaofen LI, John STELLWAGEN, Francesco MANONI, Kexue LI, Brian Alan LANMAN, Ryan Paul Wurz, Wei ZHAO, Huan RUI, Josephine ESHON
  • Patent number: 12186755
    Abstract: Described herein are multi-well separation devices configured to allow a composition comprising a target agent to be separated into multiple wells, subdivided, recombined into a single well, and/or re-separated into the same or a different configuration of wells. Also described herein are reagent loading devices configured to simultaneously deliver one or more test agents to a plurality of volumes without having to individually deliver the test agents. Together, these devices allow high throughput parallel processes without repetitive pipetting or liquid handling robotics, though they may also be used separately. Also described herein are kits and systems for chemical or biological assays, as well as methods for using the multi-well separation devices and reagent loading devices described herein.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 7, 2025
    Assignee: DrugArray, Inc.
    Inventors: Ning Chen, Robert Keith Shanahan, Dayu Teng, Daniel Joseph Braun
  • Patent number: 12189960
    Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 7, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
  • Publication number: 20250001104
    Abstract: An apparatus for use in aerosol delivery has a housing with a first rigid shell; a second rigid shell; and a deformable band coupling the first and the second rigid shells together to allow axial translation therebetween while advantageously preventing the ingress of debris or other contaminants into the housing. The housing has a cavity sized to accommodate a spray bottle therein. Pinching the rigid shells of the housing together causes operative engagement of a piston or pump of the spray bottle to dispense an aerosol, for instance to hydrate and/or deliver a physiological salt (e.g., CaCl2) to an upper respiratory tract. The housing may allow replacement of the spray bottle (e.g., sterile fill reservoir), for instance as the contents thereof are depleted. Registration features can ensure that a nozzle of the spray bottle aligns with a port in the housing.
    Type: Application
    Filed: June 16, 2022
    Publication date: January 2, 2025
    Inventors: Robert Brunner, Zu-Ning Chen, Emerson Holladay
  • Patent number: 12176559
    Abstract: The present disclosure relates to the technical field of energy storage devices, and provides a battery cell assembly, a battery module, and a battery pack. The battery cell assembly includes: at least two battery cells and an insulation film. The at least two battery cells are stacked. Each battery cell includes an electrode assembly and a battery housing. The electrode assembly is accommodated in the battery housing. The electrode assembly includes a first electrode plate, a second electrode plate, and a separator disposed between the first electrode plate and the second electrode plate. The insulation film surrounds a periphery of the at least two battery cells to wrap the at least two battery cells together.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: December 24, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY (HONG KONG) LIMITED
    Inventors: Zhenhua Li, Haizu Jin, Dongyang Shi, Ning Chen, Fei Hu, Yuanbao Chen
  • Publication number: 20240420282
    Abstract: Systems are configured for performing super-resolution processing for applications by a plurality of different hardware processing units that include hardware processing units that are native to the applications and hardware processing units that are non-native to the applications. Interfaces in the system generate different sets of instructions that are submitted to the different processing units with synchronization objects that synchronize the execution of the instructions.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventors: Shawn Lee HARGREAVES, William John KRISTIANSEN, Larry Nai-Ning CHEN, Luke Jonathan OLSEN
  • Publication number: 20240417412
    Abstract: The present disclosure provides compounds useful for the inhibition of KRAS G12D. The compounds have a general Formula I: wherein the variables of Formula I are defined herein. This disclosure also provides pharmaceutical compositions comprising the compounds, uses of the compounds, and compositions for treatment of, for example, cancer.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 19, 2024
    Applicant: AMGEN INC.
    Inventors: Brian Alan Lanman, Wei Zhao, Ryan Paul Wurz, Primali Vasundera NAVARATNE, Liping PETTUS, Michael M. YAMANO, Ning Chen, Rene RAHIMOFF, Francesco MANONI, John STELLWAGEN
  • Publication number: 20240420281
    Abstract: Systems are configured for performing super-resolution processing for applications by a plurality of different hardware processing units that include hardware processing units that are native to the applications and hardware processing units that are non-native to the applications. Interfaces in the system generate different sets of instructions that are submitted to the different processing units with synchronization objects that synchronize the execution of the instructions.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventors: Shawn Lee HARGREAVES, William John KRISTIANSEN, Larry Nai-Ning CHEN, Luke Jonathan OLSEN
  • Publication number: 20240387272
    Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Inventors: Zhen-Nong Wu, Mao-Chia Wang, Jia-Ren Chen, Li-Yi Chen, Wen Han Hung, Che-Li Lin, Yen-Ning Chen
  • Publication number: 20240379817
    Abstract: A semiconductor structure includes a p-type metal-oxide semiconductor (PMOS) region and an n-type metal-oxide semiconductor (NMOS) region, first source/drain (S/D) features in the PMOS region and second S/D features in the NMOS region, a first channel region connecting the first S/D features and a second channel region connecting the second S/D features, a first high-k metal gate stack (HKMG) over the first channel region and a second HKMG over the second channel region, first gate spacers on sidewalls of the first HKMG and second gate spacers on sidewalls of the second HKMG, a first etch-stop layer (ESL) on the first S/D features and the first gate spacers and a second ESL on the second S/D features and the second gate spacers, an oxide layer on the first ESL but not the second ESL, and an interlayer dielectric (ILD) layer on the oxide layer and the second ESL.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Bwo-Ning CHEN, Xusheng WU, Chang-Miao LIU, Shih-Hao LIN
  • Patent number: 12142638
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Hsuan Hsiao, Winnie Victoria Wei-Ning Chen, Tung Ying Lee
  • Publication number: 20240363751
    Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Winnie Victoria Wei-Ning CHEN, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20240363417
    Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Sathaiya Mahaveer DHANYAKUMAR, Huicheng CHANG, Keng-Chu LIN, Winnie Victoria Wei-Ning CHEN
  • Publication number: 20240350610
    Abstract: The present invention relates to the field of animal health. Particularly, the present invention relates to a recombinant classical swine fever virus E2 protein comprising at least one mutation at the epitope specifically recognized by the 6B8 monoclonal antibody. Further, the present invention provides an immunogenic composition comprising the recombinant E2 protein of the present invention and the use of the immunogenic composition for preventing and/or treating diseases associated with CSFV in an animal. Moreover, the present invention provides a method and a kit for differentiating animals infected with CSFV from animals vaccinated with the immunogenic composition of the present invention. Furthermore, the present invention provides a method of producing the E2 protein.
    Type: Application
    Filed: October 19, 2021
    Publication date: October 24, 2024
    Inventors: Ning Chen, Huanhuan Liu, Chao Tong, Jiaying Wang
  • Patent number: 12113118
    Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Shih-Hao Lin
  • Publication number: 20240332089
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Publication number: 20240313126
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanowire over a semiconductor fin. The semiconductor structure also includes a second nanowire over the first nanowire and a third nanowire over the second nanowire. The semiconductor structure further includes a source/drain wrapping around the first nanowire, the second nanowire and the third nanowire. A thickness of a first portion of the source/drain vertically sandwiched between the first nanowire and the second nanowire is different from a thickness of a second portion of the source/drain vertically sandwiched between the second nanowire and the third nanowire.
    Type: Application
    Filed: May 22, 2024
    Publication date: September 19, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan HSIAO, Wei-Sheng YUN, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE, Ling-Yen YEH
  • Patent number: 12083121
    Abstract: Provided herein are KRAS G12C inhibitors, such as composition of the same, and methods of using the same. These inhibitors are useful for treating a number of disorders, including pancreatic, colorectal, and lung cancers.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: September 10, 2024
    Assignee: Amgen Inc.
    Inventors: John Gordon Allen, Brian Alan Lanman, Jian Chen, Anthony B. Reed, Victor J. Cee, Longbin Liu, Patricia Lopez, Ryan Paul Wurz, Thomas T. Nguyen, Shon Booker, Jennifer Rebecca Allen, Margaret Chu-Moyer, Albert Amegadzie, Ning Chen, Clifford Goodman, Jonathan D. Low, Vu Van Ma, Ana Elena Minatti, Nobuko Nishimura, Alexander J. Pickrell, Hui-Ling Wang, Youngsook Shin, Aaron C. Siegmund, Kevin C. Yang, Nuria A. Tamayo, Mary Walton, Qiufen Xue
  • Patent number: D1057420
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: January 14, 2025
    Assignee: Apple Inc.
    Inventors: Christina J. Smiechowski, Duy P. Le, Jeffrey Scott Croyle, Matthew Phillip Casebolt, Matthew Vincent Costello, Christopher Wiita, Elvin Chu, Guillaume Raoult, Zu-Ning Chen, Christopher Kuh, Robert Brunner
  • Patent number: D1059627
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 28, 2025
    Assignee: HANGZHOU BIGFISH BIO-TECH CO., LTD.
    Inventors: Lianyi Xie, Peng Wang, Wenyu Ren, Xiaojuan Xu, Ning Chen