Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.

Abstract: A network device receives, from a congestion controller, traffic policy information associated with a data stream between a sender and a receiver, where the traffic policy information includes a maximum round trip delay time (RTT) and a maximum throughput rate (Rate). The network device obtains a receiver advertised window size (RWND) for the receiver for the data stream. The network device modifies the RWND based on the RTT and the Rate to produce a modified receiver window size (RWND?) and sends the RWND? to the sender for use in controlling congestion on the data stream between the sender and the receiver.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature electrically coupled to the vertical stack of channel members, a silicide layer formed on more than one side of the source/drain feature, and a source/drain contact electrically coupled to the source/drain feature via the silicide layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.

Abstract: Provided herein are KRAS G12C inhibitors, composition of the same, and methods of using the same. These inhibitors are useful for treating a number of disorders, including pancreatic, colorectal, and lung cancers.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: Related to is a bidirectional CLLC circuit with a coupled inductor, which is associated with a circuit topology and operation control of a bidirectional CLLC resonant converter. Provided is a structure of a bidirectional CLLC resonant circuit with a coupled inductor, including a primary side bridge, a secondary side bridge, a primary side resonant capacitor, a secondary side resonant capacitor, a coupled resonant inductor, and a transformer. Compared with a structure of a conventional bidirectional CLLC resonant circuit, two separate resonant inductors located at a primary side and a secondary side in an original resonant cavity are replaced with one coupled resonant inductor in the circuit; the coupled resonant inductor has opposite dotted terminals with the transformer, and a primary side and a secondary side of the coupled resonant inductor are respectively in serial connection with a primary side and a secondary side of the transformer.

Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.

Abstract: The present application relates to a secondary battery and a battery module. The secondary battery comprises: a casing, which is provided with an accommodating hole with an opening; a top cover assembly, which is in sealed connection with the casing to close the opening; an electrode assembly, which is arranged in the accommodating hole, and comprises two end faces opposite to a first direction perpendicular to an axial direction of the accommodating hole, and tabs extending from the end faces, the electrode assembly comprises two or more electrode units, wherein two or more electrode units are stacked in the axial direction, and in a second direction perpendicular to the axial direction and the first direction, the size of the tabs is smaller than that of the end faces; and a current collector, which comprises a body portion.

Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units.

Abstract: A resin composition and a cured film are provided. The resin composition includes a resin (A), a crosslinking agent (B), a surfactant (C), an additive (D) and a solvent (E). The resin (A) includes at least one of a phenol-based resin (A-1) and a polystyrene resin including a hydroxyl group (A-2). The additive (D) includes a fluoro-based phenol (D-1), a polyhydroxyphenol resin (D-2), a compound including an epoxy group (D-3), a polyether resin (D-4), a thermal acid generator including a sulfonate ion (D-5), or a combination thereof.

Abstract: A system, method and a tangible, non-transitory computer readable medium adapted to be executed by a processor for providing contrast enhanced ultrasound (CEUS) images is described. The CEUS system includes an ultrasound probe adapted to provide the ultrasound images; a processor; a tangible, non-transitory computer-readable medium that stores instructions, which when executed by the processor causes the processor to: determine out-of-plane frames of the ultrasound images; remove the out-of-plane frames from the ultrasound images based on a criterion to provide an optimized set of frames; and a display in communication with the processor and configured to display the optimized set of frames.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: An apparatus for processing ultrasound scan data comprises a processor configured to obtain three-dimensional ultrasound scan data for a volume including a region of interest in a subject, the processor is further configured to: provide the three-dimensional ultrasound scan data for display to the user by providing for display to the user a first two-dimensional view of the region of interest in a predetermined direction such that the first two-dimensional view intersects the first boundary; and upon receiving, via the user interface, a user input indicating a location of the first boundary in the first two-dimensional view of the region of interest, generate a second two-dimensional view of the region of interest corresponding to the slice at the first boundary on basis of the indicated location, and providing for display to the user the second two-dimensional view of the region of interest.

Abstract: Methods, systems, and devices for performing an access operation on a memory cell, incrementing a value of a first counter based on performing the access operation on the memory cell, determining that the incremented value of the first counter satisfies a threshold, incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold, and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold are described.

Abstract: An etchant composition, a tackifier, an alkaline solution, a method of removing polyimide and an etching process are provided. The etchant composition includes a tackifier (A) and an alkaline solution (B). The tackifier (A) includes a resin containing a hydroxyl group (a), a surfactant (b) and a first solvent (c1). The alkaline solution (B) includes an alkaline compound (d) and a second solvent (c2).

Abstract: Novel cultivars of Stevia rebaudiana plant, with a novel genetic trait of self-compatibility, and the advantageous use of this genetic trait in Stevia crossing breeding for increasing steviol glycosides production, including food and beverage products and other consumables, are disclosed.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.