Abstract: According to some embodiments, a motor controller for controlling a motor includes a position interface configured to receive a motor position signal indicative of a position of the motor, and a pulse width modulation (PWM) unit configured to generate a PWM signal for driving the motor. An angle and speed unit is configured to determine a speed and a position of the motor based on transitions in the motor position signal, wherein transition intervals are defined between the transitions, determine a PWM count of cycles in the PWM signal during a first transition interval of the transition intervals, and update the position of the motor during a second transition interval of the transition intervals based on the PWM count to generate an updated position. A controller is configured to send a control signal for controlling the motor to the PWM unit based on the speed and the updated position.

Abstract: According to some embodiments, a method for controlling a motor comprises receiving mechanical angle data and electrical angle data representing a position of the motor, setting an encoder offset between the mechanical angle data and the electrical angle data, determining extremum values of a phase current of the motor, adjusting the encoder offset based on the extremum values to generate an adjusted encoder offset, determining an estimated motor position and an estimated motor speed based on the mechanical angle data, the electrical angle data, and the adjusted encoder offset, and generating a drive signal for the motor based on the estimated motor position and the estimated motor speed.

Abstract: Methods and apparatus configured to obtain a decision-point value, and send, for a logical channel group (LCG) having a quantity of data pending an uplink transmission, a long buffer status report in response to the decision-point value exceeding a threshold value, or a short buffer status report in response to the decision-point value being equal to or less than the threshold value are disclosed. The decision-point value may be a buffer status report-type determinative value, which may be based on a peak power envelope of a wireless communication device, a data transmission rate historically obtained by the wireless communication device, a number of component carriers available for a complete upload of a buffer holding data, a cost function, an amount of data associated with the LCG that is pending the uplink transmission, a type of the wireless communication device, or a latency of communications of the wireless communication device.

Abstract: A method and a system for providing one or more services to one or more user devices [202] in an IoT network in a scalable M2M (Machine to Machine) framework. The method comprises receiving a connection request from the one or more user devices [202] at a load balance of the IoT network, the connection request comprises at least a username comprising a cluster identifier. The load balancer [204] determines a cluster identifier based on the connection request and identifies at least one target cluster from the one or more clusters [206], said target cluster being associated with the identifier cluster identifier. The load balancer [204] routes the connection request to the at least one target cluster to provide the one or more services to the one or more user devices [202].

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit communications on a primary component carrier and a secondary component carrier (SCC). The UE may refrain from transmission on the SCC based at least in part on an error rate for transmission on the SCC and an amount of transmission power headroom for the UE. Numerous other aspects are provided.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a measurement configuration for a plurality of cells. The UE may perform measurement of each of the plurality of cells in an order, wherein the order is based at least in part on a priority, wherein the priority is based at least in part on an aggregated downlink bandwidth. The UE may transmit a measurement report based at least in part on the order. Numerous other aspects are described.

Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for receiving an aggregate bandwidth configuration including, a downlink (DL) bandwidth configuration indicating DL resources for one or more DL receptions, and an uplink (UL) bandwidth configuration indicating UL resources for one or more UL transmissions, calculating a maximum power reduction backoff value based on the UL bandwidth configuration, and transmitting UL information for at least one of the one or more UL transmissions based on the maximum power reduction backoff value.

Abstract: A pool cleaner with a cover assembly that includes a bottom cover with a cover opening, a supply mast, a distributor manifold, a timer assembly, a scrubber assembly, and a venturi vacuum. The distributor manifold receives water from the supply mast and encircles the suction mast. The venturi vacuum is in fluid communication with the distributor manifold and is designed to vacuum debris from a pool surface.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a measurement configuration for a plurality of cells. The UE may perform measurement of each of the plurality of cells in an order, wherein the order is based at least in part on a priority, wherein the priority is based at least in part on an aggregated downlink bandwidth. The UE may transmit a measurement report based at least in part on the order. Numerous other aspects are described.

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

Abstract: Methods and apparatus configured to obtain a decision-point value, and send, for a logical channel group (LCG) having a quantity of data pending an uplink transmission, a long buffer status report in response to the decision-point value exceeding a threshold value, or a short buffer status report in response to the decision-point value being equal to or less than the threshold value are disclosed. The decision-point value may be a buffer status report-type determinative value, which may be based on a peak power envelope of a wireless communication device, a data transmission rate historically obtained by the wireless communication device, a number of component carriers available for a complete upload of a buffer holding data, a cost function, an amount of data associated with the LCG that is pending the uplink transmission, a type of the wireless communication device, or a latency of communications of the wireless communication device.

Abstract: Methods, systems, and devices for wireless communications are described. A wireless device may receive a control signal that indicates a radio resource management (RRM) configuration associated with one or more measurement thresholds for managing wireless communication links at the wireless device. The wireless device may then perform measurements for one or more synchronization signals in accordance with the RRM configuration. The wireless device may then apply an opportunistic gain to the measurements to generate modified measurements based on a quantity of radio frequency (RF) chains usable by the wireless device for communicating via the wireless communication links. The wireless device may then transmit a measurement report based on the modified measurements satisfying the one or more measurement thresholds, and may receive an additional control signal instructing the wireless device to manage the wireless communication links based on the measurement report.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.