Patents by Inventor Nitin Agarwal
Nitin Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626841Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.Type: GrantFiled: December 29, 2020Date of Patent: April 11, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nitin Agarwal, Aniruddha Roy
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Patent number: 11595011Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.Type: GrantFiled: January 12, 2021Date of Patent: February 28, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suresh Mallala, Nitin Agarwal
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Publication number: 20230043133Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.Type: ApplicationFiled: September 6, 2022Publication date: February 9, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Nitin Agarwal, Aniruddha Roy, Preetham Narayana Reddy
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Publication number: 20230033234Abstract: A bone graft generation and delivery process can include inserting bone material into an impactor system. The process can include processing, via the impactor system, the bone material into bone graft material. Processing the bone material can include milling the bone material via a first rotational element of the impactor system. Processing the bone material can include cutting the bone material via a second rotational element of the impactor system. Processing the material can include filtering the cut and milled bone material to isolate bone graft material. The process can include delivering, via the impactor system, the bone graft material to a target site.Type: ApplicationFiled: April 8, 2022Publication date: February 2, 2023Inventors: Nitin Agarwal, Jacob Rahul Rajiv Joseph, Stephen N. Housley, David Wu
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Publication number: 20230027004Abstract: A system and method for manufacturing engineered human lymphocytes for cell therapies, including isolating targeted cells of interest from apheresis starting material using an acoustic separation device and activating the targeted cells of interest in situ with, in certain aspects, antibody-coated surface in an enclosed vessel. Also, the method includes transfecting the targeted cells of interest with construct-encoded lentiviral vectors, retroviral vectors, adeno-associated vectors or non-viral vectors in the enclosed vessel. The cells of interest may then be transfected with viral or non-viral genetic material using an electroporation device. Transfected cells may then be expanded to a desired dose using an expansion feeding method. Also, the method may include combining the targeted cells of interest with cryoprotectant reagents and buffers to create a final formulation.Type: ApplicationFiled: June 29, 2022Publication date: January 26, 2023Inventors: Nathaniel W. Freund, Kaiyuan Jiang, Suchit Sahai, Hsing-Chuan Tsai, Maolu Li, Joshua Ray Plat, Waleed Haso, Nitin Agarwal, Qi Cai, Luis Diaz, Kent S. Young
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Publication number: 20230021963Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.Type: ApplicationFiled: May 30, 2022Publication date: January 26, 2023Inventors: Nitesh Singhal, Parijat Sinha, Nitin Agarwal, Muthukumar Murugesan
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Patent number: 11558013Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.Type: GrantFiled: December 3, 2019Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nitin Agarwal, Kunal Karanjkar, Venkata Ramanan
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Patent number: 11558488Abstract: A method and a system for providing one or more services to one or more user devices [202] in an IoT network in a scalable M2M (Machine to Machine) framework. The method comprises receiving a connection request from the one or more user devices [202] at a load balance of the IoT network, the connection request comprises at least a username comprising a cluster identifier. The load balancer [204] determines a cluster identifier based on the connection request and identifies at least one target cluster from the one or more clusters [206], said target cluster being associated with the identifier cluster identifier. The load balancer [204] routes the connection request to the at least one target cluster to provide the one or more services to the one or more user devices [202].Type: GrantFiled: December 31, 2020Date of Patent: January 17, 2023Inventors: Vishal Rajani, Wai Yin Yee, Mahesh Jena, Nitin Agarwal, Prateek Agarwal
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Publication number: 20230006663Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Applicant: Texas Instruments IncorporatedInventors: Nitin Agarwal, Venkat Ramakrishna Saripalli, Venkata Ramanan R
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Publication number: 20220392432Abstract: Systems and methods for speech recognition correction include receiving a voice recognition input from an individual user and using a trained error correction model to add a new alternative result to a results list based on the received voice input processed by a voice recognition system. The error correction model is trained using contextual information corresponding to the individual user. The contextual information comprises a plurality of historical user correction logs, a plurality of personal class definitions, and an application context. A re-ranker re-ranks the results list with the new alternative result and a top result from the re-ranked results list is output.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Inventors: Issac ALPHONSO, Tasos ANASTASAKOS, Michael LEVIT, Nitin AGARWAL
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Publication number: 20220345086Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.Type: ApplicationFiled: October 25, 2021Publication date: October 27, 2022Inventors: Nitin AGARWAL, Aniruddha ROY, Preetham NARAYANA REDDY
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Publication number: 20220334196Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin on the chip, and where the pin is adapted to be coupled to an external resistor, where the external resistor is external to the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first switch, and a second capacitor coupled to a second switch. The oscillator circuit includes leakage circuitry coupled to the current mirror, where the leakage circuitry is configured to draw a current from the current mirror proportional to a leakage current flowing through the external resistor from circuitry internal to the chip.Type: ApplicationFiled: October 25, 2021Publication date: October 20, 2022Inventors: Aniruddha ROY, Nitin AGARWAL, Preetham NARAYANA REDDY
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Publication number: 20220302906Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventors: Aniruddha ROY, Nitin AGARWAL, Rajavelu THINAKARAN
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Patent number: 11448672Abstract: A meter case used with a utility meter is disclosed. The meter shell includes a plurality of snap fit joints assembled on the meter case arranged to engage a module cover to mount the module cover to the meter shell. The module cover further includes wire housing formed along an inner periphery of the module cover that houses a wire having a first end and a second end therein. A metal shield placed behind the meter shell is electrically coupled to a first connector. A terminal electrically connected to the metal shield is arranged to discharge current to ground. An electrical contact electrically coupled to the second end of the wire is arranged to engage the first connector to establish an electrical connection to the metal shield for the discharge to ground of electrostatic currents sensed by wire.Type: GrantFiled: December 15, 2020Date of Patent: September 20, 2022Assignee: Honeywell International Inc.Inventors: Nitin Agarwal, Murali Krishna Bezawada, Murajith Menon, Krishna Mohan, Suresh Kumar Palle, Ganesh Patil, Vidyadhar Patwardhan, S Piramanayagam, Shalu Singhvi
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Patent number: 11444612Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.Type: GrantFiled: April 6, 2021Date of Patent: September 13, 2022Assignee: Texas Instruments IncorporatedInventors: Nitin Agarwal, Venkat Ramakrishna Saripalli, Venkata Ramanan R
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Patent number: 11437955Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.Type: GrantFiled: October 25, 2021Date of Patent: September 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nitin Agarwal, Aniruddha Roy, Preetham Narayana Reddy
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Patent number: 11387814Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.Type: GrantFiled: August 31, 2020Date of Patent: July 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aniruddha Roy, Nitin Agarwal, Rajavelu Thinakaran
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Publication number: 20220187348Abstract: A meter case used with a utility meter is disclosed. The meter shell includes a plurality of snap fit joints assembled on the meter case arranged to engage a module cover to mount the module cover to the meter shell. The module cover further includes wire housing formed along an inner periphery of the module cover that houses a wire having a first end and a second end therein. A metal shield placed behind the meter shell is electrically coupled to a first connector. A terminal electrically connected to the metal shield is arranged to discharge current to ground. An electrical contact electrically coupled to the second end of the wire is arranged to engage the first connector to establish an electrical connection to the metal shield for the discharge to ground of electrostatic currents sensed by wire.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Applicant: Honeywell International Inc.Inventors: Nitin Agarwal, Murali Krishna Bezawada, Murajith Menon, Krishna Mohan, Suresh Kumar Palle, Ganesh Patil, Vidyadhar Patwardhan, S Piramanayagam, Shalu Singhvi
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Patent number: 11348150Abstract: A system and method for facilitating electronic commerce over a network, according to one or more embodiments, includes communicating with a user via a user device and an issuer of payment media via an issuer device over the network, the payment media being issued to the user by the issuer, receiving user instruction over the network to link the payment media to a user account related to the user, prompting the user over the network to input a secure password known only by the issuer and the user, receiving the secure password from the user over the network, verifying that the payment media is owned by the user over the network via a secure protocol, returning a response to the user related to verification of the payment media, and storing payment media verification information.Type: GrantFiled: October 15, 2019Date of Patent: May 31, 2022Assignee: PayPal, Inc.Inventors: Nitesh Singhal, Parijat Sinha, Nitin Agarwal, Muthukumar Murugesan
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Publication number: 20220129024Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Inventors: Sachin Sudhir Turkewadikar, Nitin Agarwal, Madhan Radhakrishnan