Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit communications on a primary component carrier and a secondary component carrier (SCC). The UE may refrain from transmission on the SCC based at least in part on an error rate for transmission on the SCC and an amount of transmission power headroom for the UE. Numerous other aspects are provided.

Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

Abstract: A pool cleaner with a cover assembly that includes a bottom cover with a cover opening, a supply mast, a distributor manifold, a timer assembly, a scrubber assembly, and a venturi vacuum. The distributor manifold receives water from the supply mast and encircles the suction mast. The venturi vacuum is in fluid communication with the distributor manifold and is designed to vacuum debris from a pool surface.

Abstract: A method and a system for providing one or more services to one or more user devices [202] in an IoT network in a scalable M2M (Machine to Machine) framework. The method comprises receiving a connection request from the one or more user devices [202] at a load balance of the IoT network, the connection request comprises at least a username comprising a cluster identifier. The load balancer [204] determines a cluster identifier based on the connection request and identifies at least one target cluster from the one or more clusters [206], said target cluster being associated with the identifier cluster identifier. The load balancer [204] routes the connection request to the at least one target cluster to provide the one or more services to the one or more user devices [202].

Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

Abstract: A pool cleaner comprises a housing including at least two wheels, a supply mast, and a timer disc assembly configured to receive water from the supply mast. The timer disc assembly includes an outer housing, a plurality of outlet ports extending through the outer housing, and a rotating timer disc positioned within the outer housing adjacent to the plurality of outlet ports. The timer disc assembly also includes at least one stationary port seal liner positioned between one of the plurality of outlet ports and the rotating timer disc. The at least one stationary port seal liner includes an elastomeric piece and a liner piece, and the liner piece is in contact with the rotating timer disc.

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

Abstract: A meter casing can include a metal shield, and an outer casing that includes a display screen cavity that maintains a display screen, an optical port cavity that houses an optical port sensor assembly including a dongle, and a seal button cavity that houses a seal button and a sealing element. The seal button cavity can include one or more recess cavities formed in the communications module cover. The optical port cavity can include a circular port to securely mount the dongle. In addition, snap joints can be provided, which can hold an optical port cover that covers the optical port with respect to the optical port cavity.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A method for facilitating the exchange of a stable cryptocurrency collateralized by government-issued debt. First granularity parameters are received through a first wallet interface of a first digital wallet. A first restricted use key is generated based upon the first granularity parameters and provided to an owner of a second digital wallet. A second restricted use key is generated based upon second granularity parameters received through a second wallet interface associated with the second digital wallet. Information from a blockchain wallet is accessed using the second restricted use key wherein the information relates to one or more of an ID classification and risk score of the second wallet owner at a level of detail determined by the second granularity parameters. An indication to proceed with a transaction between the first digital wallet and the second digital wallet may then be received through the first wallet interface.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.