Abstract: A detection mechanism includes a light source disposed on a substrate, a condensing lens disposed between the substrate and light emitted from the light source, and a photodetector disposed on the substrate and under the condensing lens.

Abstract: A detection mechanism includes a light source disposed on a substrate, a condensing lens disposed between the substrate and light emitted from the light source, and a photodetector disposed on the substrate and under the condensing lens.

Abstract: A gas sensor includes: a sensor surface on which a metal-oxide film grows; a detection unit configured to detect a change in a resistance value of the metal-oxide film; and a computation unit configured to compute a quantity of reducing gas in measurement-target air based on a result of the detection by the detection unit, wherein the gas sensor operates in a first mode in which the gas sensor stands by with standby air, which differs from the measurement-target air, being in contact with the sensor surface immediately after the gas sensor is activated and in a second mode that follows the first mode and in which, the detection unit detects a change in the resistance value, and the computation unit computes the quantity of the reducing gas based on the result of the detection, with the measurement-target air being in contact with the sensor surface.

Abstract: A detection device according to an aspect of the invention, includes: a housing including an air intake port and an air discharge port; a platelike member having a first air ventilation port and a second air ventilation port, the platelike member being provided inside the housing; a first sensor provided on an air intake port side of the first air ventilation port on a front face of the platelike member; and a second sensor provided between the first air ventilation port and the second air ventilation port on a rear face of the platelike member.

Abstract: A detection mechanism includes a light source disposed on a substrate, a condensing lens disposed between the substrate and light emitted from the light source, and a photodetector disposed on the substrate and under the condensing lens.

Abstract: A particulate detection sensor that detects concentration of a particulate in a fluid includes a light emitting element, a SPAD array light detecting unit, and a signal processing unit. The signal processing unit calculates the concentration of the particulate based on a first pulse count value in a lighting period and a second pulse count value in a lighting-off period.

Abstract: Each stage of a gate driver includes a controlling part which increases an electric potential of a boosting line in response to a carry signal of a previous stage and decreases the electric potential of the boosting line in response to the carry signal of a next stage, a first output part which turns on in response to the increased electric potential of the boosting line and receiving a clock signal to output a gate signal of a present stage, and a second output part which turns on in response to the increased electric potential of the boosting line and receiving the clock signal to output the carry signal of the present stage. The boosting line of the present stage is disposed adjacent to a gate line which is connected to one of next stages following the present stage.

Abstract: A particulate detection sensor that detects concentration of a particulate in a fluid includes a light emitting element, a SPAD array light detecting unit, and a signal processing unit. The signal processing unit calculates the concentration of the particulate based on a first pulse count value in a lighting period and a second pulse count value in a lighting-off period.

Abstract: A gate driving circuit includes a plurality of stages. A k-th stage from among the plurality of stages, the k-th stage includes a first input circuit to receive a (k?1)th gate signal from a (k?1)th stage and to precharge a first node, a second input circuit to receive a (k+2)th gate signal from a (k+2)th stage to transmit the received (k+2)th gate signal to a second node, an output circuit to output a first clock signal as a k-th gate signal in response to a signal of the first node, a discharge circuit configured to discharge the first node through the k-th gate signal in response to a signal of the second node, a first transfer circuit to transfer a second clock signal to the first node, and a second transfer circuit to transfer the first clock signal to the second node.

Abstract: A display device with space for accommodating elements of a gate driver in a display area of the display device, the display device including first and second adjacent pixel electrodes, and third and fourth adjacent pixel electrodes; a gate line extending between the first pixel electrode and the second pixel electrode and between the third pixel electrode and the fourth pixel electrode; a gate driver having a plurality of elements and configured to drive the gate line; and a light blocking layer overlapping the gate line, wherein the light blocking layer comprises a first light blocking portion and a second light blocking portion, the first light blocking portion is adjacent to the first pixel electrode and the second pixel electrode, the second light blocking portion is adjacent to the third pixel electrode and the fourth pixel electrode, the second light blocking portion having a larger size than a size of the first light blocking portion, and at least one of the plurality of elements of the gate driver ov

Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

Abstract: A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.

Abstract: Each stage of a gate driver includes a controlling part which increases an electric potential of a boosting line in response to a carry signal of a previous stage and decreases the electric potential of the boosting line in response to the carry signal of a next stage, a first output part which turns on in response to the increased electric potential of the boosting line and receiving a clock signal to output a gate signal of a present stage, and a second output part which turns on in response to the increased electric potential of the boosting line and receiving the clock signal to output the carry signal of the present stage. The boosting line of the present stage is disposed adjacent to a gate line which is connected to one of next stages following the present stage.

Abstract: A display device with space for accommodating elements of a gate driver in a display area of the display device, the display device including first and second adjacent pixel electrodes, and third and fourth adjacent pixel electrodes; a gate line extending between the first pixel electrode and the second pixel electrode and between the third pixel electrode and the fourth pixel electrode; a gate driver having a plurality of elements and configured to drive the gate line; and a light blocking layer overlapping the gate line, wherein the light blocking layer comprises a first light blocking portion and a second light blocking portion, the first light blocking portion is adjacent to the first pixel electrode and the second pixel electrode, the second light blocking portion is adjacent to the third pixel electrode and the fourth pixel electrode, the second light blocking portion having a larger size than a size of the first light blocking portion, and at least one of the plurality of elements of the gate driver ov

Abstract: A gate driving circuit includes a plurality of stages. A k-th stage from among the plurality of stages, the k-th stage includes a first input circuit to receive a (k?1)th gate signal from a (k?1)th stage and to precharge a first node, a second input circuit to receive a (k+2)th gate signal from a (k+2)th stage to transmit the received (k+2)th gate signal to a second node, an output circuit to output a first clock signal as a k-th gate signal in response to a signal of the first node, a discharge circuit configured to discharge the first node through the k-th gate signal in response to a signal of the second node, a first transfer circuit to transfer a second clock signal to the first node, and a second transfer circuit to transfer the first clock signal to the second node.

Abstract: A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

Abstract: A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.

Abstract: A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value.