Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Abstract: In a gain variable amplifier, a carrier detection circuit system, and an infrared remote-control receiver using the gain variable amplifier or the carrier detection circuit system, to each of a positive output voltage Vo1 and a negative output voltage Vo2 of an amp to be subjected to gain control, connected is an AGC circuit output current (½) Iagc which is one-half of a gain control current and is a constant current. With this arrangement, it is possible to provide the gain variable amplifier, the carrier detection circuit system, both of which can reduce noise superimposed on the gain control current, and it is also possible to provide the infrared remote-control receiver using the gain variable amplifier or the carrier detection circuit system.

Abstract: A semiconductor memory device including: a semiconductor substrate; a plurality of memory cells arranged in a matrix having columns and rows on the semiconductor substrate and each including a source, a drain and a control gate; a plurality of insulative device isolation layers positioned in a surface portion of the substrate as extending in a column direction for isolating the memory cells arranged in each row of the matrix; a plurality of word lines positioned on the substrate as extending in a row direction and each constituted by the control gates of the memory cells of the each row which are connected in series; the source and the drain of each of the memory cells of the each row being positioned in the surface portion of the substrate on opposite sides of a corresponding one of the word lines between an adjacent pair of insulative device isolation layers; and a common source line positioned on the substrate between an adjacent pair of word lines with the intervention of side wall films positioned on sid

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.

Abstract: A semiconductor device comprising a memory cell which includes: a pillar-shaped semiconductor layer of a first conductive type formed on a semiconductor substrate; source and drain diffusion layers of a second conductive type formed in upper and lower portions of the pillar-shaped semiconductor layer; a semiconductor layer of the second conductive type or a cavity formed inside the pillar-shaped semiconductor layer; and a gate electrode formed on a side face of the pillar-shaped semiconductor layer via a gate insulating film, or a control gate electrode formed on the side face of the pillar-shaped semiconductor layer via a charge accumulation layer.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A conventional carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is arranged to charge and discharge in the following manner, an integration capacitor in an integrator that performs the integral action. Namely, the integration capacitor is (i) either charged or discharged in accordance with a result of the discrimination of the reception signal at the carrier detection level, or (ii) charged in accordance with the result of the discrimination while the integration capacitor is constantly discharged at a constant level. In contrast, a carrier detecting circuit of the present invention is arranged so that the integration capacitor is both charged and discharged constantly at a level that varies in accordance with the result of the discrimination.

Abstract: The present invention provides a semiconductor memory device comprising one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein

Abstract: A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.

Abstract: A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

Abstract: The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Abstract: A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.

Abstract: A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.

Abstract: A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A method of straightening a wire rod of titanium or titanium alloy wherein the rod is hot-straightened to a straight rod at the straightening temperature T and elongation .epsilon. satisfying the expression (1) or (2). The method includes hot rolling a titanium billet of .beta. titanium alloy, (.alpha.+.beta.) titanium alloy or a near .alpha. titanium alloy into a wire rod, winding the hot rolled wire rod into a coil, cold drawing the wire rod, cutting the wire rod to obtain a bent wire rod, heating the bent wire rod to a straightening temperature T while both end portions of the bent wire rod are fixed, applying a predetermined elongation .epsilon. to the wire rod, maintaining a straightening temperature T, hot-straightening the wire in accordance with the expression (2).epsilon.(T-400).gtoreq.400 (1).epsilon.(T-500).gtoreq.200 (2)and cooling the wire rod while applying tension. The method is suitable for preparing a straight rod for use in an engine valve.