Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A solid-state image capturing apparatus includes a pixel array in which a plurality of pixels are arranged in a matrix, where each of the pixels includes: a photodiode for obtaining a signal charge by a photoelectric conversion of an incident light; and an amplifying transistor for the signal charge obtained at the photodiode, and where the amplifying transistor is configured in such a manner that a gate area of the amplifying transistor is defined to be larger than a gate area of other transistors that configure the pixel.

Abstract: A solid-state image capturing element according to the present invention is provided, in which one or a plurality of light receiving sections for photoelectrically converting an incident light to generate a signal charge is provided on a surface of a semiconductor area or a surface of a semiconductor substrate and a peripheral circuit with a transistor is provided, where a reflection preventing film provided above the light receiving sections and a gate sidewall film of the transistor are formed with a common nitride film that is formed simultaneously.

Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.

Abstract: A solid-state image capturing device is provided with a plurality of light receiving elements arranged on a surface section of a semiconductor substrate, a color filter of each color for each of the plurality of light receiving elements, and a plurality of microlenses each for condensing incident light into each of the plurality of light receiving elements, in which the interlayer insulation film is provided directly below the color filter of each color in a state where a passivation and hydrogen sintering process film is removed from the interlayer insulation film.

Abstract: A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.

Abstract: A comparing circuit of the present invention includes: a charging and discharging circuit to charge a capacitor with charging current and discharge the capacitor with discharging current alternately in response to a switch of an input pulse signal; a comparator circuit to compare a capacitor-voltage (Csig) of the capacitor with a first threshold voltage (Vth1) and the capacitor-voltage (Csig) with a second threshold voltage (Vth2), which is higher than the first threshold voltage, to generate a pulse signal responsive to a result of this comparison, and to supply an output-signal generating circuit with the pulse signal to switch a level of an output pulse-signal; and a logical operation circuit to adjust a value of the charging current and a value of the discharging current by generating a signal that is based on the pulse signal and is to adjust the value of the charging current and the value of the discharging current of the charging and discharging circuit and supplying the charging and discharging circui

Abstract: A carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is disclosed and includes an integration capacitor that is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit, where the charging circuit and the discharging circuit are provided in an integrator which performs the integral action.

Abstract: A semiconductor wafer of the present invention includes switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad. The semiconductor wafer also includes switch control pads which are provided in the scribing region or the semiconductor chips. Voltages of the switch control pads are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer. The switch control pads are provided with signals whose voltages are different from the substrate voltage so that the switch circuits are turned on. Moreover, each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.

Abstract: A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern except for the portions of the first insulating film corresponding to the upper electrodes, a second insulating film covering at least another metal pattern except for the portions of the second insulating film corresponding to the external terminals, and a semiconductor element connected to the upper electrodes and placed on the substrate for semiconductor device. The solder-connected surface of the external terminal is positioned to have a height larger than that of a surface of the second insulating film. The semiconductor element is placed on the first insulating film and covered, together with the upper electrodes, with a mold resin.

Abstract: A semiconductor-element mounting substrate is a substrate for mounting a semiconductor element, and includes a substrate body. The substrate body has a mounting surface, and the center portion of the mounting surface is provided with a die pattern. Through conductors are provided in a portion of the substrate body located outside the die pattern to penetrate the substrate body in the thicknesswise direction. First terminals and second terminals are connected to the through conductors, respectively. The first terminals each extend toward the outer edge of the mounting surface, and they are electrically connected to the semiconductor element. The second terminals are provided on a surface of the substrate body opposite to the mounting surface.

Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.

Abstract: A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.