Patents by Inventor Nobuaki Hashimoto

Nobuaki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic substrate, semiconductor device, and electronic device
    Patent number: 7746232
    Abstract: An electronic substrate including: a base substrate having an active face and a rear face; and a plurality of inductor elements formed on or above the active face, or formed on or above the rear face.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: June 29, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • SEMICONDUCTOR DEVICE
    Publication number: 20100155945
    Abstract: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes.
    Type: Application
    Filed: March 8, 2010
    Publication date: June 24, 2010
    Applicant: Seiko Epson Corporation
    Inventor: Nobuaki HASHIMOTO
  • SEMICONDUCTOR DEVICE
    Publication number: 20100155944
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.
    Type: Application
    Filed: March 8, 2010
    Publication date: June 24, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • ELECTRONIC COMPONENT, CIRCUIT BOARD, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
    Publication number: 20100134993
    Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.
    Type: Application
    Filed: January 28, 2010
    Publication date: June 3, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Haruki ITO, Nobuaki HASHIMOTO
  • ELECTRONIC COMPONENT, MOUNTING STRUCTURE THEREOF, AND METHOD FOR MOUNTING ELECTRONIC COMPONENT
    Publication number: 20100109484
    Abstract: An electronic component includes: a functional piece having a predetermined function; a bump electrode formed on the functional piece, the bump electrode including a core with elastic property and a conductive film provided on a surface of the core; and a holding unit for holding a conductive contact state between the bump electrode and a connecting electrode which is electrically conducted to a driving circuit. The electronic component is coupled to the connecting electrode, and elastic deformation of the core causes the conductive film to make conductive contact with the connecting electrode.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Applicant: Seiko Epson Corporation
    Inventor: Nobuaki HASHIMOTO
  • Semiconductor device
    Patent number: 7705454
    Abstract: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: April 27, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Semiconductor device
    Patent number: 7705453
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: April 27, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • ELECTRONIC COMPONENT MOUNTING STRUCTURE
    Publication number: 20100071946
    Abstract: An electronic component mounting structure includes: an electronic component including a plurality of bump electrodes that includes a base resin provided on an active face of the electronic component and a plurality of conductive films that cover a part of a surface of the base resin, expose an area excluding the part of the surface, and are electrically coupled to a plurality of electrode terminals provided on the active face; and a substrate including a plurality of terminals.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 25, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Sealed surface acoustic wave element package
    Patent number: 7679153
    Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: March 16, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument
    Patent number: 7662673
    Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: February 16, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
    Patent number: 7659142
    Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: February 9, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Electronic substrate manufacturing method
    Patent number: 7645706
    Abstract: An electronic substrate manufacturing method includes: forming a wiring pattern on a substrate; providing a mask with an opening for the substrate on which the wiring pattern has been formed; performing a specified treatment in a part area of the wiring pattern through the opening of the mask. The opening has a size based on an accuracy of an alignment between the substrate and the mask.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: January 12, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, CIRCUIT BOARD MOUNTED WITH THE SAME, AND ELECTRONIC APPLIANCE COMPRISING THE CIRCUIT BOARD
    Publication number: 20090302467
    Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.
    Type: Application
    Filed: August 18, 2009
    Publication date: December 10, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument
    Patent number: 7611925
    Abstract: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 3, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
    Patent number: 7598619
    Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 6, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Electronic board, method of manufacturing the same, and electronic device
    Patent number: 7598459
    Abstract: An electronic board includes: a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor that has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: October 6, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Electronic device and method of manufacturing the same, circuit board, and electronic instrument
    Patent number: 7564142
    Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: July 21, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument
    Publication number: 20090181521
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 16, 2009
    Applicant: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Semiconductor device and method of manufacture thereof, circuit board and electronic instrument
    Patent number: 7560819
    Abstract: A semiconductor device, including a semiconductor chip having electrodes, a substrate having an interconnect pattern, and an adhesive, the adhesive having a first portion and a second portion, the first portion interposed between a surface of the substrate on which the interconnect pattern is formed and a surface of the semiconductor chip on which the electrodes are formed, the second portion not overlapping with the semiconductor chip. Further disclosed is the semiconductor device mounted on the circuit board and an electronic instrument having the semiconductor device.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: July 14, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Semiconductor device, circuit board, and electronic instrument
    Publication number: 20090174068
    Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).
    Type: Application
    Filed: March 6, 2009
    Publication date: July 9, 2009
    Applicant: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto