Patents by Inventor Nobuaki Hashimoto

Nobuaki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8097817
    Abstract: An electronic component includes: a first substrate having a through-hole; a second substrate opposite the first substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; a functional element having at least a part thereof disposed in the sealing space, and a through-electrode filling the through-hole, the through-hole penetrating the first substrate. The sealing member includes an elastic core part on the first substrate. A metal film is on a surface of the core part and is bonded to the second substrate.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: January 17, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8080447
    Abstract: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: December 20, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20110266690
    Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 3, 2011
    Applicant: Seiko Epson Corporation
    Inventors: Haruki ITO, Nobuaki HASHIMOTO
  • Patent number: 8012864
    Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 6, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 8004077
    Abstract: A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: August 23, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Publication number: 20110180927
    Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 28, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20110136337
    Abstract: A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi TANAKA, Nobuaki HASHIMOTO
  • Publication number: 20110095422
    Abstract: An electronic component including an electronic element, an electrode that is formed on a first surface of the electronic element, a first resin layer that is formed over the first surface of the electronic element, a wiring that is electrically connected to the electrode, a first portion of the wiring extending over the first resin layer, a second resin layer that is formed over the first resin layer and the wiring, the second resin layer having an opening, the opening overlapping the first portion of the wiring, an external terminal that is provided above the second resin layer, the external terminal being connected to the first portion of the wiring via the opening, and a third resin layer that is formed over the second resin layer, the third resin layer being provided around the external terminal.
    Type: Application
    Filed: January 3, 2011
    Publication date: April 28, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20110095432
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Application
    Filed: January 7, 2011
    Publication date: April 28, 2011
    Applicant: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7932612
    Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: April 26, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20110079898
    Abstract: A substrate includes an insulating film in which a penetrating hole is formed, the penetrating hole extending between a first surface of the insulating film and a second surface of the insulating film opposite to the first surface of the insulating film. A wiring pattern is adhered to the first surface of the insulating film by an adhesive material. A first portion of the wiring pattern is formed over the penetrating hole, and a part of the adhesive material is formed on an internal wall surface forming the penetrating hole so as not to stop up the penetrating hole. An external electrode contacts the first portion of the wiring pattern and projects through the penetrating hole and extends beyond the second surface of the insulating film.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 7, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki Hashimoto
  • Publication number: 20110074250
    Abstract: A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the first substrate and the second substrate while disposing at least a part of a functional element within a space between the first region and the second region; obtaining a plurality of first divisional substrates by cutting the first substrate at each of the first regions, after the connecting of the first substrate and the second substrate; forming a sealing film covering the plurality of the first divisional substrates on the second substrate, after cutting the first substrate; obtaining a plurality of second divisional substrates by cutting the second substrate at each of the second regions, after forming the sealing film; and obtaining a plurality of individual electronic devices.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Patent number: 7910498
    Abstract: A method for manufacturing a semiconductor device, including: (a) forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; (b) fusing the resin layer without being cured and shrunk by a first energy supply processing; (c) forming a resin boss by curing and shrinking the resin layer after fusion by a second energy supply processing; and (d) forming an electrical conducting layer which is electrically connected to the electrode pad and passes through over the resin boss.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: March 22, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi Tanaka, Nobuaki Hashimoto
  • Publication number: 20110062534
    Abstract: An electronic component includes: a first substrate having a through-hole; a second substrate opposite the first substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; a functional element having at least a part thereof disposed in the sealing space, and a through-electrode filling the through-hole, the through-hole penetrating the first substrate. The sealing member includes an elastic core part on the first substrate. A metal film is on a surface of the core part and is bonded to the second substrate.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 17, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20110062566
    Abstract: A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals.
    Type: Application
    Filed: November 17, 2010
    Publication date: March 17, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Haruki ITO, Nobuaki HASHIMOTO
  • Patent number: 7888177
    Abstract: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: February 15, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7888260
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: February 15, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7871858
    Abstract: A method of manufacturing a semiconductor device forms a penetrating hole in a substrate so that the penetrating hole extends from a first surface of the substrate to a second surface of the substrate being opposite to the first surface. An internal wall surface of the penetrating hole has a protrusion formed of a material constituting the substrate, the first surface of the substrate being closer to the protrusion than the second surface. A conductive member is formed on the first surface so that the conductive member covers the penetrating hole. A semiconductor chip is mounted on the first surface so that an electrode of the semiconductor chip is electrically connected to the conductive member. An external electrode is provided through the penetrating hole so that the external electrode is electrically connected to the conductive member and the external electrode projects from the second surface of the substrate.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: January 18, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7868466
    Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material between a substrate and a semiconductor chip; a second step in which pressure and heat are applied between the semiconductor chip and the substrate, an interconnect pattern and electrodes are electrically connected, and the anisotropic conductive material is spreading out beyond the semiconductor chip and is cured in the region of contact with the semiconductor chip; and a third step in which the region of the anisotropic conductive material other than the region of contact with the semiconductor chip is heated.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 11, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7867830
    Abstract: A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the first substrate and the second substrate while disposing at least a part of a functional element within a space between the first region and the second region; obtaining a plurality of first divisional substrates by cutting the first substrate at each of the first regions, after the connecting of the first substrate and the second substrate; forming a sealing film covering the plurality of the first divisional substrates on the second substrate, after cutting the first substrate; obtaining a plurality of second divisional substrates by cutting the second substrate at each of the second regions, after forming the sealing film; and obtaining a plurality of individual electronic devices.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 11, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto