Patents by Inventor Nobuaki Hashimoto

Nobuaki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120236301
    Abstract: A measurement apparatus for measuring the concentration of a target substance contained in a sample includes: a light source (light source device); a light-incident body (sensor chip) that has a sample contact surface, where an enhanced electric field is formed by metal particles, and enhances Raman scattering light radiated from the target substance by light emitted from the light source in the enhanced electric field; an irradiation unit that causes the light emitted from the light source to enter into a plurality of areas in the light-incident body; a light-receiving unit (light-receiving element) that receives the Raman scattering light radiated from a plurality of the areas; and a quantitative measurement unit (control device) that quantitatively measures a concentration of the target substance based on a total number of the areas and a strength of the Raman scattering light received from the areas.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 20, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20120235261
    Abstract: A via hole is formed on a base substrate before a device circuit is formed, and thermal oxidation is performed to form a thermal oxidation layer on a surface of the base substrate on which the device circuit is formed and a surface in the via hole. The device circuit having a conductive section is formed on the base substrate after the thermal oxidation, and then, a conductive body is embedded in the via hole.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 20, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Tsuyoshi YODA, Nobuaki HASHIMOTO
  • Patent number: 8231197
    Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 31, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8227914
    Abstract: A mounting structure of an electronic component includes: a substrate having a terminal and the electronic component which is mounted on the substrate; and a bump electrode included in the electronic component. This bump electrode has an underlying resin provided on an active surface of the electronic component, and a conductive film covering part of a surface of the underlying resin and exposing the rest so as to be electrically continued to an electrode terminal. In this mounting structure, the conductive film of the bump electrode makes direct conductive contact with the terminal, and the underlying resin of the bump electrode elastically deforms so that at least part of an exposed area which is exposed without being covered by the conductive film directly adheres to the substrate. Further, the substrate and the electronic component retain a state of the bump electrode making conductive contact with the terminal by adhesivity of the exposed area of the underlying resin to the substrate.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: July 24, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8227878
    Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: July 24, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Patent number: 8191247
    Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: June 5, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8178968
    Abstract: An electronic component includes: an active surface; a plurality of external connection terminals included in the active surface; a bump electrode disposed to the active surface, the bump electrode including: an internal resin formed on the active surface as a core; and a conductive film on a surface of the internal resin, the internal resin being formed in a nearly half-cylindrical shape having a transverse section of one of a nearly semicircular shape, a nearly semielliptical shape, and a nearly trapezoidal shape and extending orthogonal to the transverse section, the transverse section being orthogonal to the active surface; and a global wiring line disposed on the active surface and connecting between the plurality of external connection terminals, and at least one of the external connection terminals being electrically connected to the conductive film.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: May 15, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20120103673
    Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20120091860
    Abstract: An electronic component includes: a functional piece having a predetermined function; a bump electrode formed on the functional piece, the bump electrode including a core with elastic property and a conductive film provided on a surface of the core; and a holding unit for holding a conductive contact state between the bump electrode and a connecting electrode which is electrically conducted to a driving circuit. The electronic component is coupled to the connecting electrode, and elastic deformation of the core causes the conductive film to make conductive contact with the connecting electrode.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 19, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20120086088
    Abstract: An electronic component includes: a first substrate having a through-hole; a second substrate opposite the first substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; a functional element having at least a part thereof disposed in the sealing space, and a through-electrode filling the through-hole, the through-hole penetrating the first substrate. The sealing member includes an elastic core part on the first substrate. A metal film is on a surface of the core part and is bonded to the second substrate.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Patent number: 8143728
    Abstract: An electronic board includes: a substrate; and a wiring pattern provided on the substrate and having a part that forms a resistance element, the part having wiring specifications that are different from those of other parts.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: March 27, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8138612
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: March 20, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8134237
    Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 13, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20120052634
    Abstract: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 1, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Patent number: 8114788
    Abstract: A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: February 14, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi Tanaka, Nobuaki Hashimoto
  • Patent number: 8115284
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: February 14, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8115309
    Abstract: A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes an electrical connection section disposed on one of the resin protrusions. At least part of the resin protrusions are disposed in a region near a short side of the surface and extend in a direction which intersects the short side.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 14, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8110245
    Abstract: There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: February 7, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8106304
    Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: January 31, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8102099
    Abstract: An electronic component includes: a functional piece having a predetermined function; a bump electrode formed on the functional piece, the bump electrode including a core with elastic property and a conductive film provided on a surface of the core; and a holding unit for holding a conductive contact state between the bump electrode and a connecting electrode which is electrically conducted to a driving circuit. The electronic component is coupled to the connecting electrode, and elastic deformation of the core causes the conductive film to make conductive contact with the connecting electrode.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: January 24, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto