Patents by Inventor Nobuaki Hashimoto

Nobuaki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863529
    Abstract: An electronic component includes: a first substrate; a second substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; and a functional element at least a part of which is disposed in the sealing space. In the electronic component, the sealing member includes a core part formed on the first substrate and having elasticity and a metal film formed on a surface of the core part, and the metal film is bonded to the second substrate.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: January 4, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7850295
    Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed, and a rear face that is on a side opposite to the active element formation face; a penetration electrode penetrating the semiconductor substrate; an element electrode formed on or above the active element formation face; detection electrodes formed on or above the rear face, electrically connected to the element electrode via the penetration electrode, and detecting a remaining amount of the ink by being wet in the ink; a storage circuit storing the remaining amount of ink; an antenna formed on either one of the active element formation face and the rear face, transmitting and receiving information; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: December 14, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7851912
    Abstract: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: December 14, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20100304533
    Abstract: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 2, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Patent number: 7842598
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Publication number: 20100273311
    Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 28, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100258901
    Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 14, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100252925
    Abstract: A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes an electrical connection section disposed on one of the resin protrusions. At least part of the resin protrusions are disposed in a region near a short side of the surface and extend in a direction which intersects the short side.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 7, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100254113
    Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.
    Type: Application
    Filed: June 14, 2010
    Publication date: October 7, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100237749
    Abstract: An electronic component includes: a functional piece having a predetermined function; a bump electrode formed on the functional piece, the bump electrode including a core with elastic property and a conductive film provided on a surface of the core; and a holding unit for holding a conductive contact state between the bump electrode and a connecting electrode which is electrically conducted to a driving circuit. The electronic component is coupled to the connecting electrode, and elastic deformation of the core causes the conductive film to make conductive contact with the connecting electrode.
    Type: Application
    Filed: June 3, 2010
    Publication date: September 23, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100240176
    Abstract: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 23, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki Hashimoto
  • Publication number: 20100226109
    Abstract: An electronic substrate includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100223784
    Abstract: An electronic substrate includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Publication number: 20100219927
    Abstract: An electronic substrate including: a base substrate having an active face and a rear face; and a plurality of inductor elements formed on or above the active face, or formed on or above the rear face.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Nobuaki HASHIMOTO
  • Patent number: 7780281
    Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 24, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7777332
    Abstract: A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes an electrical connection section disposed on one of the resin protrusions. At least part of the resin protrusions are disposed in a region near a short side of the surface and extend in a direction which intersects the short side.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: August 17, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7760512
    Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: July 20, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7755261
    Abstract: An electronic component includes: a functional piece having a predetermined function; a bump electrode formed on the functional piece, the bump electrode including a core with elastic property and a conductive film provided on a surface of the core; and a holding unit for holding a conductive contact state between the bump electrode and a connecting electrode which is electrically conducted to a driving circuit. The electronic component is coupled to the connecting electrode, and elastic deformation of the core causes the conductive film to make conductive contact with the connecting electrode.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: July 13, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7755205
    Abstract: The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 13, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7746663
    Abstract: An electronic substrate is disclosed that includes: a substrate having a first face on which an active region is formed, and a second face on an opposite side to the first face and on which a passive element is formed. The substrate may further include: a penetrative conductive portion penetrating through the substrate; and an electrode formed on the first face, wherein the passive element is electrically connected to the electrode via a penetrative conductive portion.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 29, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto