Abstract: To provide a ceramic particle separable composite material having a calcium phosphate sintered body particle with which bioaffinity reduction and solubility change are suppressed as much as possible and which has a smaller particle diameter. A ceramic particle separable composite material comprising a ceramic particle and a substrate, wherein: the ceramic particle and the substrate are chemically bonded to each other, or the ceramic particle physically adheres to or is embedded in the substrate; the ceramic particle has a particle diameter within a range of 10 nm to 700 nm; the ceramic particle is a calcium phosphate sintered body particle; and the ceramic particle contains no calcium carbonate.

Abstract: This invention has an object to provide a means for providing a calcium phosphate sintered body particle group that does not cause a phenomenon of bubble generation in any use mode thereof, and further has a smaller particle diameter. There is provided a ceramic particle group containing spherical ceramic particles, which is characterized in that the ceramic particle has a particle diameter within a range of 10 nm to 700 nm, and is a calcium phosphate sintered body particle, and further the ceramic particle group contains no calcium carbonate.

Abstract: This invention has an object to provide a means for providing a calcium phosphate sintered body particle group that does not cause a phenomenon of bubble generation in any use mode thereof, and further has a smaller particle diameter. There is provided a ceramic particle group containing spherical ceramic particles, which is characterized in that the ceramic particle has a particle diameter within a range of 10 nm to 700 nm, and is a calcium phosphate sintered body particle, and further the ceramic particle group contains no calcium carbonate.

Abstract: It is an object of the present invention to provide a ceramic particle carrying medical tube and/or cuff excellent in cell adhesive property and the like. A medical tube and/or cuff carrying a ceramic particle in at least a part thereof, wherein: the ceramic particle has a particle diameter within a range of 10 nm to 700 nm; the ceramic particle is a calcium phosphate sintered body particle; and the ceramic particle contains no calcium carbonate.

Abstract: This invention has an object to provide a means for providing a calcium phosphate sintered body particle group that does not cause a phenomenon of bubble generation in any use mode thereof, and further has a smaller particle diameter. There is provided a ceramic particle group containing spherical ceramic particles, which is characterized in that the ceramic particle has a particle diameter within a range of 10 nm to 700 nm, and is a calcium phosphate sintered body particle, and further the ceramic particle group contains no calcium carbonate.

Abstract: To provide a novel stent which is excellent in cell adhesive property and the like. A stent carrying a ceramic particle, wherein: the ceramic particle has a particle diameter within a range of 10 nm to 700 nm; the ceramic particle is a calcium phosphate sintered body particle; and the ceramic particle contains no calcium carbonate.

Abstract: To provide a ceramic particle separable composite material having a calcium phosphate sintered body particle with which bioaffinity reduction and solubility change are suppressed as much as possible and which has a smaller particle diameter. A ceramic particle separable composite material comprising a ceramic particle and a substrate, wherein: the ceramic particle and the substrate are chemically bonded to each other, or the ceramic particle physically adheres to or is embedded in the substrate; the ceramic particle has a particle diameter within a range of 10 nm to 700 nm; the ceramic particle is a calcium phosphate sintered body particle; and the ceramic particle contains no calcium carbonate.

Abstract: A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.

Abstract: A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes.

Abstract: A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region.

Abstract: A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.

Abstract: The interlayer insulating film of this invention is composed of a polymer in which a first monomer having four substituted acetylenyl groups and polymerizable in the three-dimensional direction and a second monomer having two substituted cyclopentanonyl groups and polymerizable in the two-dimensional direction are three-dimensionally polymerized.

Abstract: In a method of forming an interlayer insulating film by plasma CVD, an organic siloxane compound including one or more silicon atoms each having at least three or more units each represented by a general formula, —O—Si(R1R2)—OR3 (wherein R1 and R2 are the same as or different from each other and are a methyl group, an ethyl group or a propyl group, and R3 is the same as or different from R1 and R2 and is a methyl group, an ethyl group, a propyl group or a phenyl group) is used as a raw material.

Abstract: An interlayer dielectric film is made from an organic/inorganic hybrid film. The organic/inorganic hybrid film has a main chain in which a first site of siloxane and a second site of an organic molecule are alternately bonded to each other.

Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).

Abstract: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.

Abstract: A semiconductor device includes a first substrate formed with a through silicon via reaching the back surface thereof, and a second substrate electrically connected to the first substrate via the through silicon via, and bonded to the back surface of the first substrate. A taper angle of a sidewall of a tip end portion of the through silicon via connected to the second substrate is larger than a taper angle of a sidewall of the other portion thereof.

Abstract: At least three or more plurality of chips are stacked to form a three-dimensional integrated circuit. When the plurality of chips are stacked, at least two or more of three stacking methods are used which are a wafer-to-wafer stacking method that bonds together the mutually corresponding chips each on a wafer level, a chip-to-wafer stacking method that bonds together the mutually corresponding chips including one on a chip level and the other on a wafer level, and a chip-to-chip stacking method that bonds together the mutually corresponding chips each on a chip level.

Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).

Abstract: In the multilayered interconnect structure, an upper-layer interconnect is formed in an interlayer dielectric film formed on a lower-layer interconnect of copper, and the lower-layer interconnect and the upper-layer interconnect of copper are connected to each other through a via formed in the interlayer dielectric film. A layer of the interlayer dielectric film in contact with the lower-layer interconnect is made of a layer including, as a principal component, an aromatic compound containing a nitrogen atom having a lone pair of electrons in an aromatic ring.