Patents by Inventor Nobuo Aoi

Nobuo Aoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100087059
    Abstract: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 8, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Nobuo Aoi
  • Patent number: 7691453
    Abstract: A method for forming an organic/inorganic hybrid insulation film includes the following steps. An organic silicon compound containing siloxane bonds is vaporized, the vaporized organic silicon compound is transported to a reaction chamber maintaining the compound in a monomer state, and then, the organic/inorganic hybrid insulation film having a main chain structure where siloxane parts and organic molecule parts are alternately combined on a substrate installed in the reaction chamber is formed by plasma-polymerizing the vaporized organic silicon compound in the reaction chamber.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 6, 2010
    Assignee: Panasonic Corporation
    Inventor: Nobuo Aoi
  • Patent number: 7663239
    Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ikeda, Hideo Nakagawa, Nobuo Aoi
  • Patent number: 7659626
    Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried metal interconnect 8 formed in the insulation film 6, and a barrier metal film 7 formed between the insulation film 6 and the metal interconnect 8. The barrier metal film 7 is a metal compound film. The metal compound film is characterized by including at least one of elements forming the insulation film.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: February 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideo Nakagawa, Atsushi Ikeda, Nobuo Aoi
  • Patent number: 7648908
    Abstract: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: January 19, 2010
    Assignee: Panasonic Corporation
    Inventor: Nobuo Aoi
  • Publication number: 20090298298
    Abstract: In a method of forming an interlayer insulating film by plasma CVD, an organic siloxane compound including one or more silicon atoms each having at least three or more units each represented by a general formula, —O—Si(R1R2)—OR3 (wherein R1 and R2 are the same as or different from each other and are a methyl group, an ethyl group or a propyl group, and R3 is the same as or different from R1 and R2 and is a methyl group, an ethyl group, a propyl group or a phenyl group) is used as a raw material.
    Type: Application
    Filed: March 13, 2006
    Publication date: December 3, 2009
    Applicant: PANASONIC CORPORATION
    Inventor: Nobuo Aoi
  • Publication number: 20090266590
    Abstract: An interconnect structure includes: an interlayer insulating film formed on a lower metal layer; a contact hole formed in the interlayer insulating film to expose the lower metal layer; a plurality of carbon nanotubes formed on a bottom of the contact hole; an wiring metal filled in the contact hole to fill gap between the plurality of carbon nanotubes; and an upper wiring formed above the contact hole. A Ti layer is formed between the plurality of carbon nanotubes and the upper wiring.
    Type: Application
    Filed: June 2, 2009
    Publication date: October 29, 2009
    Applicant: PANASONIC CORPORATION
    Inventor: Nobuo AOI
  • Publication number: 20090098726
    Abstract: After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Inventor: Nobuo AOI
  • Publication number: 20090042403
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a nitrogen-containing layer in an exposed portion of a copper interconnect formed in an insulating film provided on a substrate; and forming an interlayer insulating film on the nitrogen-containing layer through plasma CVD performed by using, as a material, an organic silicon compound having a siloxane (Si—O—Si) bond.
    Type: Application
    Filed: October 2, 2008
    Publication date: February 12, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Nobuo Aoi, Hideo Nakagawa
  • Patent number: 7396778
    Abstract: A Lewis acid-base reaction is caused, in a solution, between a first monomer corresponding to a Lewis acid and a second monomer corresponding to a Lewis base, so as to generate a monomer adduct in which the first monomer and the second monomer are bonded to each other through weak electric interaction. Next, the solution including the monomer adduct is applied on a substrate so as to form a supramolecular solid thin film made of the monomer adduct. Then, the supramolecular solid thin film is heated so as to cause a polymerization reaction between the first monomer and the second monomer within the supramolecular solid thin film, thereby forming a polymer thin film.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: July 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20080150151
    Abstract: In the multilayered interconnect structure, an upper-layer interconnect is formed in an interlayer dielectric film formed on a lower-layer interconnect of copper, and the lower-layer interconnect and the upper-layer interconnect of copper are connected to each other through a via formed in the interlayer dielectric film. A layer of the interlayer dielectric film in contact with the lower-layer interconnect is made of a layer including, as a principal component, an aromatic compound containing a nitrogen atom having a lone pair of electrons in an aromatic ring.
    Type: Application
    Filed: March 30, 2006
    Publication date: June 26, 2008
    Inventor: Nobuo Aoi
  • Publication number: 20080090094
    Abstract: An interlayer dielectric film is made from an organic/inorganic hybrid film. The organic/inorganic hybrid film has a main chain in which a first site of siloxane and a second site of an organic molecule are alternately bonded to each other.
    Type: Application
    Filed: December 10, 2007
    Publication date: April 17, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Nobuo Aoi
  • Publication number: 20080083989
    Abstract: A semiconductor device includes insulation films (6 and 8) formed over a silicon substrate (1), a buried wire (14) formed in the insulation films (6 and 8), and a barrier metal film (A1) formed between each of the insulation films (6 and 8) and the buried wire (14). The barrier metal film (A1) is formed of a metal oxide film (11), a transition layer (12a) and a metal film (13) stacked in this order in the direction from a side of the barrier metal film (A1) at which the insulation films (6 and 8) exists to a side thereof at which the buried wire (14) exists. The transition layer (12a) is formed of a single atomic layer having substantially an intermediate composition between respective compositions of the metal oxide film (11) and the metal film (13).
    Type: Application
    Filed: May 20, 2005
    Publication date: April 10, 2008
    Inventors: Nobuo Aoi, Hideo Nakagawa, Atsushi Ikeda
  • Publication number: 20080054464
    Abstract: In a semiconductor device including: an insulating film (6) formed over a substrate (1); a buried metal interconnect (10) formed in the insulating film (6); and a barrier metal film (A1) formed between the insulating film (6) and the metal interconnect (10), the barrier metal film (A1) includes a metal oxide film (7), a metal compound film (8) and a metal film (9) stacked in this order from a side in which the insulating film (6) exists to a side in which the metal interconnect (10) exists. Elastic modulus of the metal compound film (8) is larger than that of the metal oxide film (7).
    Type: Application
    Filed: May 20, 2005
    Publication date: March 6, 2008
    Inventors: Atsushi Ikeda, Hideo Nakagawa, Nobuo Aoi
  • Patent number: 7291919
    Abstract: The interlayer dielectric film made of a three-dimensionally polymerized polymer is formed by polymerizing: first cross-linking molecules having three or more sets of functional groups in one molecule providing a three-dimensional structure; and a second cross-linking molecule having two sets of functional groups in one molecule providing a two-dimensional structure. In the three-dimensionally polymerized polymer, dispersed are a number of molecular level pores formed by the polymerization of the first and second cross-linking molecules.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: November 6, 2007
    Assignee: Matsushita ELectrical Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20070213488
    Abstract: The interlayer insulating film of this invention is composed of a polymer in which a first monomer having four substituted acetylenyl groups and polymerizable in the three-dimensional direction and a second monomer having two substituted cyclopentanonyl groups and polymerizable in the two-dimensional direction are three-dimensionally polymerized.
    Type: Application
    Filed: May 11, 2007
    Publication date: September 13, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Nobuo Aoi
  • Publication number: 20070191585
    Abstract: A method for forming an organic polymer film includes a step of polymerizing a monomer including an adamantane derivative in which a substituent group having a carbon number of 1 or more, a functional group or a functional group bonded to a substituent group is bonded to at least the 1-, 3-, 5- and 7-positions of an adamantane skeleton.
    Type: Application
    Filed: February 14, 2007
    Publication date: August 16, 2007
    Inventor: Nobuo Aoi
  • Patent number: 7232874
    Abstract: The interlayer insulating film of this invention is composed of a polymer in which a first monomer having four substituted acetylenyl groups and polymerizable in the three-dimensional direction and a second monomer having two substituted cyclopentanonyl groups and polymerizable in the two-dimensional direction are three-dimensionally polymerized.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: June 19, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20070132100
    Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried interconnect 10 formed in the insulation film 6, and a barrier metal film A1 formed between the insulation film 6 and the buried interconnect 10. The barrier metal film A1 is formed of a lamination layer of a metal compound film 7 and a metal film 9 which does not loose its conductivity when being oxidized. In the vicinity of an interface between the metal compound film 7 and the metal film 9, a fusion layer 8 obtained through fusion of the metal compound film 7 and the metal film 9 is provided.
    Type: Application
    Filed: May 20, 2005
    Publication date: June 14, 2007
    Inventors: Atsushi Ikeda, Hideo Nakagwa, Nobuo Aoi
  • Publication number: 20070108616
    Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried metal interconnect 8 formed in the insulation film 6, and a barrier metal film 7 formed between the insulation film 6 and the metal interconnect 8. The barrier metal film 7 is a metal compound film. The metal compound film is characterized by including at least one of elements forming the insulation film.
    Type: Application
    Filed: May 20, 2005
    Publication date: May 17, 2007
    Inventors: Hideo Nakagawa, Atsushi Ikeda, Nobuo Aoi