Patents by Inventor Nobuo Aoi

Nobuo Aoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6602802
    Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: August 5, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Patent number: 6558756
    Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula: R1xSi(OR2)4-x (where R1 is a phenyl group or a vinyl group; R2 is an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where R1 is a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where R1 is a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: May 6, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
  • Patent number: 6545361
    Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 8, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Publication number: 20030017718
    Abstract: A method for forming an interlayer dielectric film includes the step of forming the interlayer dielectric film out of an organic/inorganic hybrid film by plasma-polymerizing a source material, including an organosilicon compound, at a relatively high pressure within an environment containing nitrogen gas as a dilute gas.
    Type: Application
    Filed: August 21, 2002
    Publication date: January 23, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Nobuo Aoi
  • Publication number: 20030008998
    Abstract: An interlayer dielectric film is made from an organic/inorganic hybrid film. The organic/inorganic hybrid film has a main chain in which a first site of siloxane and a second site of an organic molecule are alternately bonded to each other.
    Type: Application
    Filed: April 24, 2002
    Publication date: January 9, 2003
    Applicant: MATASUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Nobuo Aoi
  • Publication number: 20030003741
    Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.
    Type: Application
    Filed: August 19, 2002
    Publication date: January 2, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Patent number: 6458720
    Abstract: A method for forming an interlayer dielectric film includes the step of forming the interlayer dielectric film out of an organic/inorganic hybrid film by plasma-polymerizing a source material, including an organosilicon compound, at a relatively high pressure within an environment containing nitrogen gas as a dilute gas.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Patent number: 6455436
    Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: September 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Publication number: 20020119676
    Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.
    Type: Application
    Filed: April 22, 2002
    Publication date: August 29, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Patent number: 6387824
    Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: May 14, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20020034873
    Abstract: The interlayer dielectric film made of a three-dimensionally polymerized polymer is formed by polymerizing: first cross-linking molecules having three or more sets of functional groups in one molecule providing a three-dimensional structure; and a second cross-linking molecule having two sets of functional groups in one molecule providing a two-dimensional structure. In the three-dimensionally polymerized polymer, dispersed are a number of molecular level pores formed by the polymerization of the first and second cross-linking molecules.
    Type: Application
    Filed: March 16, 2001
    Publication date: March 21, 2002
    Inventor: Nobuo Aoi
  • Publication number: 20020004298
    Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:
    Type: Application
    Filed: July 9, 2001
    Publication date: January 10, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
  • Patent number: 6333257
    Abstract: An interconnection structure includes an interlevel insulating film, made of organic-containing silicon dioxide, between lower- and upper-level metal interconnects. A phenyl group, bonded to a silicon atom, is introduced into silicon dioxide in the organic-containing silicon dioxide.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: December 25, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20010051228
    Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:
    Type: Application
    Filed: July 9, 2001
    Publication date: December 13, 2001
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
  • Publication number: 20010045657
    Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.
    Type: Application
    Filed: June 18, 2001
    Publication date: November 29, 2001
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi, Hideo Nakagawa
  • Patent number: 6319854
    Abstract: An organic acid containing solution obtained by adding an organic acid having an alkyl group to a solution including silanol condensate particles is applied on a substrate so as to form a coating film. The coating film is heat treated so as to form a porous film.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: November 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Publication number: 20010026019
    Abstract: An interconnection structure includes an interlevel insulating film, made of organic-containing silicon dioxide, between lower- and upper-level metal interconnects. A phenyl group, bonded to a silicon atom, is introduced into silicon dioxide in the organic-containing silicon dioxide.
    Type: Application
    Filed: May 1, 2001
    Publication date: October 4, 2001
    Inventor: Nobuo Aoi
  • Publication number: 20010023128
    Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat
    Type: Application
    Filed: April 16, 2001
    Publication date: September 20, 2001
    Applicant: Matsushita Electrics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Patent number: 6287973
    Abstract: In a method for forming an interconnection structure, first, second and third insulating films and a thin film are sequentially formed over lower-level metal interconnects. Then, the thin film is masked with a first resist pattern and etched to form a mask pattern with openings for interconnects. Next, the third insulating film is masked with a second resist pattern and dry-etched such that the third insulating film and the first and second resist patterns are etched at a high rate and that the second insulating film is etched at a low rate to form openings for contact holes in the third insulating film and remove the first and second resist patterns. Then, the second insulating film is masked with the third insulating film and dry-etched such that the second insulating film is etched at a high rate and that the first and third insulating films are etched at a low rate to form the openings for contact holes in the second insulating film.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: September 11, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Nobuo Aoi
  • Patent number: 6242336
    Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: June 5, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi