Patents by Inventor Nobuo Sasaki

Nobuo Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4527181
    Abstract: A semiconductor device according to the present invention including a first semiconductor region formed on an insulating substrate which is a bit line and, another or second semiconductor region formed on the substrate which is a power supply line. The semiconductor device also includes an opposite conductive type semiconductor region formed on the substrate which is between the two semiconductor regions, additionally includes a metal wiring layer which is a word line and which is situated on an insulating layer on the opposite conductive type semiconductor region. The first semiconductor region bit line is in parallel with the second semiconductor region powerline which is connected to an electric power supply. The metal wiring word line being perpendicular to the second semiconductor region power line which is connected to the electric power supply.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: July 2, 1985
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4468855
    Abstract: A method for producing a semiconductor device comprising the steps of forming a gate insulating layer (3) on a semiconductor substrate having a first conductivity (1) and forming an aluminum gate electrode (4) on the gate insulating layer (3); impurity doped regions (5, 6) are then formed in the semiconductor substrate (1) by means of implantation of impurity ions having a second conductivity opposite that of the first conductivity into the semiconductor substrate (1) using the aluminum gate electrode (4) as a masking material for annealing the impurity doped regions (5, 6). The annealing process occurs by irradiating a beam on the impurity doped regions (5, 6) including the aluminum gate electrode (4). After forming the impurity doped regions (5, 6) in the semiconductor substrate (1), at least the upper surface of the aluminum gate electrode (4) is covered with an insulating layer (7).
    Type: Grant
    Filed: August 4, 1982
    Date of Patent: September 4, 1984
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4425700
    Abstract: The method of manufacture of a semiconductor device having wirings or electrodes of silicide formed by: exposing parts of a single-crystal silicon layer formed on an insulating substrate, forming a film of metal over the exposed parts, and annealing so that a silicide is formed of the silicon and metal throughout the entire thickness of the silicon layer. The single-crystal silicon layer may be formed on a sapphire or spinel substrate having a film of silicon dioxide, sapphire or spinel, epitaxially grown on a silicon substrate.
    Type: Grant
    Filed: August 7, 1981
    Date of Patent: January 17, 1984
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Motoo Nakano
  • Patent number: 4423431
    Abstract: A protective semiconductor integrated circuit device for protecting an internal circuit against an excessively high voltage has a first resistor of a low value resistance interposed between an input terminal and an input gate of the internal circuit. One of the drain and source regions of an MIS type transistor is connected to the input gate of the internal circuit to be protected and the other region of the source and drain is grounded. A capacitor is interposed between the gate of the MIS transistor and the input terminal. A second resistor or a diode of reverse polarity is interposed between the gate of the MIS transistor and ground. The protective device may be fabricated using, a bulk silicon, an insulating substrate such as sapphire, spinel or semi-insulating material, simultaneously with the internal circuit and without changing processes for fabrication of the internal circuit and without requiring any additional masking steps.
    Type: Grant
    Filed: December 24, 1980
    Date of Patent: December 27, 1983
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4404733
    Abstract: An improved contact hole in a method of producing a semiconductor device by forming a silicon dioxide insulating layer by a chemical vapor deposition method on a semiconductor substrate, forming a contact hole in the insulating layer diffusing phosphorus or boron impurities into a portion of the insulating layer around the contact hole, heating the substrate to cause plastic flow of the insulating layer; and forming a conductive layer on the insulating layer, wherein the portion of the insulating layer containing a high concentration of phosphorus or boron plastically flows during the heating step.
    Type: Grant
    Filed: January 27, 1982
    Date of Patent: September 20, 1983
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4375993
    Abstract: A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then annealing the semiconductor layer by means of a first laser with a second laser being applied to the insulator layer to heat it while the first layer is applied to the semiconductor laser.
    Type: Grant
    Filed: April 8, 1981
    Date of Patent: March 8, 1983
    Assignee: Fujitsu Limited
    Inventors: Haruhisa Mori, Hajime Kamioka, Motoo Nakano, Nobuo Sasaki
  • Patent number: 4371955
    Abstract: In a semiconductor layer of either conductivity type, a central region having a low threshold voltage and side regions having a high threshold voltage are formed between a source regio
    Type: Grant
    Filed: February 15, 1980
    Date of Patent: February 1, 1983
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4348803
    Abstract: In a process for producing a semiconductor device using an insulating substrate, a so called SOS device, a semiconductor layer is formed on the insulating film and semiconductor elements are formed in the semiconductor layer, material, which develops color with in the insulating substrate, is introduced in the substrate, and a color developed part of the insulating substrate is used as an identification mark of the substrate and the semiconductor elements. Cracking of the substrates due to formation of the identification mark is prevented.
    Type: Grant
    Filed: June 4, 1980
    Date of Patent: September 14, 1982
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4275093
    Abstract: A method of manufacturing SOS type semiconductor devices having small leakage current comprising the steps of forming a single crystal semiconductor film on an insulator single crystal substrate, selectively forming a film for masking against oxidation on the surface of the single crystal semiconductor film, and thermally oxidizing the single crystal semiconductor film, in a region which is not covered with the masking film, down to the surface of the insulating single crystal substrate in a water vapor atmosphere having a high pressure which is at least more than atmospheric pressure.
    Type: Grant
    Filed: June 13, 1979
    Date of Patent: June 23, 1981
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Yasuo Kobayashi, Ryoiku Tohgei, Takashi Iwai, Motoo Nakano
  • Patent number: 4262340
    Abstract: A semiconductor memory device provides a plurality of bit lines, a plurality of memory cells each of which is connected to a pair of different bit lines, a plurality of common word wires each of which is connected to the memory cells via a transmission gate. A characteristic feature of the present invention is to provide at least one amplifier between two memory cells which are connected to a word line or a bit line so as to prevent an increase of the access time of the memory device.
    Type: Grant
    Filed: November 9, 1979
    Date of Patent: April 14, 1981
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Yasuo Kobayashi, Takashi Iwai, Motoo Nakano
  • Patent number: 4250569
    Abstract: Disclosed is a semiconductor memory device using semiconductor memory elements as memory cells. Each semiconductor memory element is provided with a semiconductor region having a particular conductivity type, a source region and a drain region both having opposite conductivity type and both being located adjacent to the semiconductor region, one on each side of the semiconductor region, so that the semiconductor region functions as a separator between the source region and the drain region, and a gate electrode which is provided over the surface of the semiconductor region on a dielectric insulation film. In the semiconductor memory device, information is written in the semiconductor memory element by injecting electric charges into the semiconductor region, and the written information is read by detecting a variation of the electrical conductance on the surface of the semiconductor region due to the injection of electric charges.
    Type: Grant
    Filed: November 15, 1978
    Date of Patent: February 10, 1981
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Moto'o Nakano, Yasuo Kobayashi, Takashi Iwai